參數(shù)資料
型號(hào): AT17LV040-10BJC
廠商: ATMEL CORP
元件分類: PROM
英文描述: FPGA Configuration EEPROM Memory
中文描述: 4M X 1 CONFIGURATION MEMORY, PQCC44
封裝: PLASTIC, MS-018AC, LCC-44
文件頁數(shù): 6/29頁
文件大?。?/td> 412K
代理商: AT17LV040-10BJC
14
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
17. AC Characteristics
V
CC = 3.3V ± 10%
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
OE to Data Delay
50
55
50
55
ns
T
CE
CE to Data Delay
60605560
ns
T
CAC
CLK to Data Delay
75
80
55
60
ns
T
OH
Data Hold from CE, OE, or CLK
0000
ns
T
DF
CE or OE to Data Float Delay
55
50
ns
T
LC
CLK Low Time
25
ns
T
HC
CLK High Time
25
ns
T
SCE
CE Setup Time to CLK
(to guarantee proper counting)
35
60
30
35
ns
T
HCE
CE Hold Time from CLK
(to guarantee proper counting)
0000
ns
T
HOE
OE High Time (guarantees counter is reset)
25
ns
F
MAX
Maximum Clock Frequency
10
15
10
MHz
18. AC Characteristics when Cascading
V
CC = 3.3V ± 10%
Symbol
Description
AT17LV65/128/256
AT17LV512/010/002/040
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
CDF
CLK to Data Float Delay
60
50
ns
T
OCK
CLK to CEO Delay
55
60
50
55
ns
T
OCE
CE to CEO Delay
55
60
35
40
ns
T
OOE
RESET/OE to CEO Delay
40
45
35
ns
F
MAX
Maximum Clock Frequency
8
12.5
10
MHz
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