R
will be recognized by the device with the remaining LSBs being internally fixed to the logic “0”
state. Similarly, when reading from the registers, up to 12 bits of data will be output from the
device with the remaining LSBs fixed in the logic “0” state.
Table 6-11.
TLOW Limit Register and THIGH Limit Register Format
Upper Byte
Lower Byte
Resolution
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12 bits
Sign
TD
0
11 bits
Sign
TD
0
10 bits
Sign
TD
0
9 bits
Sign
TD
0
Note:
TD = Temperature Data
To set the value of either the TLOW or THIGH Limit Register, the Master must first initiate a
START condition followed by the AT30TS750’s device address byte (1001AAA0 where “AAA”
corresponds to the hard-wired A2-0 address pins). After the AT30TS750 has received the proper
address byte, the device will send an ACK to the Master.
The Master must then send the
appropriate Pointer Register byte of 02h to select the TLOW Limit Register or 03h to select the
THIGH Limit Register. After the Pointer Register byte has been sent, the AT30TS750 will send
another ACK to the Master. After receiving the ACK from the AT30TS750, the Master must then
send two data bytes to the AT30TS750 to set the value of the TLOW or THIGH Limit Register. Any
subsequent bytes sent to the AT30TS750 will simply be ignored by the device. If the Master does
not send two complete bytes of data prior to issuing a STOP or repeated START condition, then
the AT30TS750 will ignore the data and the contents of the register will not be changed.
In addition to the Master not sending two complete bytes of data, writing to the TLOW or THIGH
Limit Register will be ignored and no operation will be performed under the following conditions:
the nonvolatile registers are busy because of a copy operation (the NVRBSY bit of the
Configuration Register is in the logic “1” state), the volatile and nonvolatile registers are currently
locked (the RLCK bit of the Nonvolatile Configuration Register is in the logic “1” state), or the
volatile and nonvolatile registers are permanently locked down (the RLCKDWN bit of the
Nonvolatile Configuration Register is in the logic “1” state). However, the device will still respond
with an ACK, except in the case of the nonvolatile registers being busy, to indicate that it received
the proper data bytes even though the contents of the TLOW or THIGH Limit Register will not be
changed. In the case of the nonvolatile registers being busy, the device will respond with an ACK
to the address and pointer bytes but will then NACK when the data bytes are sent from the
Master.
In order to read the TLOW or THIGH Limit Register, the Pointer Register must be set or have been
previously set to 02h to select the TLOW Limit Register or 03h to select the THIGH Limit Register
(if the previous operation was a write to one of the registers, then the Pointer Register will already
be set for that particular limit register). If the Pointer Register has already been set appropriately,
the TLOW or THIGH Limit Register can be read by having the Master first initiate a START
condition followed by the AT30TS750’s device address byte (1001AAA1 where “AAA”
corresponds to the hard-wired A2-0 address pins). After the AT30TS750 has received the proper
address byte, the device will send an ACK to the Master. The Master can then read the upper
byte of the TLOW or THIGH Limit Register. After the upper byte of the register has been clocked
8749A-DTS-03/11
Atmel AT30TS750 [Preliminary]
28