參數(shù)資料
型號： AT40K40LV-3BGC
廠商： ATMEL CORP
元件分類： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PBGA352
封裝： BGA-352
文件頁數(shù)： 28/67頁
文件大?。?/td> 1589K
代理商： AT40K40LV-3BGC
34
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL.
All input IO characteristics measured from a V
IH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
V
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.
Cell Function
Parameter
Path
-3
Units
Notes
Repeaters
Repeater
t
PD (Maximum)
L -> E
2.2
ns
1 unit load
Repeater
tPD (Maximum)
E -> E
2.2
ns
1 unit load
Repeater
tPD (Maximum)
L -> L
2.2
ns
1 unit load
Repeater
tPD (Maximum)
E -> L
2.2
ns
1 unit load
Repeater
t
PD (Maximum)
E -> IO
1.4
ns
1 unit load
Repeater
t
PD (Maximum)
L -> IO
1.4
ns
1 unit load
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
VDD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.
Cell Function
Parameter
Path
-3
Units
Notes
IO
Input
tPD (Maximum)
pad -> x/y
1.9
ns
No extra delay
Input
tPD (Maximum)
pad -> x/y
5.8
ns
1 extra delay
Input
tPD (Maximum)
pad -> x/y
11.5
ns
2 extra delays
Input
t
PD (Maximum)
pad -> x/y
17.4
ns
3 extra delays
Output, Slow
t
PD (Maximum)
x/y/E/L -> pad
9.1
ns
50 pf load
Output, Medium
tPD (Maximum)
x/y/E/L -> pad
7.6
ns
50 pf load
Output, Fast
tPD (Maximum)
x/y/E/L -> pad
6.2
ns
50 pf load
Output, Slow
tPZX (Maximum)
oe -> pad
9.5
ns
50 pf load
Output, Slow
tPXZ (Maximum)
oe -> pad
2.1
ns
50 pf load
Output, Medium
t
PZX (Maximum)
oe -> pad
7.4
ns
50 pf load
Output, Medium
t
PXZ (Maximum)
oe -> pad
2.7
ns
50 pf load
Output, Fast
tPZX (Maximum)
oe -> pad
5.9
ns
50 pf load
Output, Fast
tPXZ (Maximum)
oe -> pad
2.4
ns
50 pf load
相關(guān)PDF資料
PDF描述
AT40K40LV-3BQC FPGA, 2304 CLBS, 40000 GATES, PQFP144
AT40K40LV-3DQC FPGA, 2304 CLBS, 40000 GATES, PQFP208
AT40K40LV-3EQC FPGA, 2304 CLBS, 40000 GATES, PQFP240
AT40K40LV-3FQC FPGA, 2304 CLBS, 40000 GATES, PQFP304
AT40KEL040KW1SB FPGA, 2304 CLBS, 50000 GATES, PQFP160
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT40K40LV-3BGI 功能描述:IC FPGA 3.3V 2304 CELL 352BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3BQC 功能描述:IC FPGA 3.3V 2304 CELL 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3BQI 功能描述:IC FPGA 3.3V 2304 CELL 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3CGC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3CQC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*