參數(shù)資料
型號： AT40K40LV-3BGC
廠商： ATMEL CORP
元件分類： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PBGA352
封裝： BGA-352
文件頁數(shù)： 56/67頁
文件大?。?/td> 1589K
代理商： AT40K40LV-3BGC
6
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
The Busing Network
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “l(fā)eapfrogs” or bypasses a repeater. Repeaters regener-
ate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programma-
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface. Express/Express turns are
implemented through separate pass gates distributed throughout the array.
Some of the bus resources on the AT40K/AT40KLV are used as a dual-function
resources. Table 2 shows which buses are used in a dual-function mode and which bus
plane is used. The AT40K/AT40KLV software tools are designed to accommodate dual-
function buses in an efficient manner.
Table 2. Dual-function Buses
Function
Type
Plane(s)
Direction
Comments
Cell Output Enable
Local
5
Horizontal
and Vertical
RAM Output Enable
Express
2
Vertical
Bus full length at array edge
Bus in first column to left of
RAM block
RAM Write Enable
Express
1
Vertical
Bus full length at array edge
Bus in first column to left of
RAM block
RAM Address
Express
1 - 5
Vertical
Buses full length at array edge
Buses in second column to left
of RAM block
RAM Data In
Local
1
Horizontal
Data In connects to local
bus plane 1
RAM Data Out
Local
2
Horizontal
Data out connects to local
bus plane 2
Clocking
Express
4
Vertical
Bus half length at array edge
Set/Reset
Express
5
Vertical
Bus half length at array edge
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT40K40LV-3BGI 功能描述:IC FPGA 3.3V 2304 CELL 352BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3BQC 功能描述:IC FPGA 3.3V 2304 CELL 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3BQI 功能描述:IC FPGA 3.3V 2304 CELL 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3CGC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3CQC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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