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參數(shù)資料
| 型號： | AT42QT1110-MZ |
| 廠商： | ATMEL CORP |
| 元件分類： | 速度傳感器和接近開關(guān) |
| 英文描述： | PROXIMITY SENSOR-CAPACITIVE, 0-5V, SQUARE, SURFACE MOUNT |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-220VHHD-2, QFN-32 |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 657K |
| 代理商： | AT42QT1110-MZ |
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35
4519 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
Table 10 Timer related registers
W21
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
Count source
System clock (STCK)
Prescaler output (ORCLK)
Timer 1 underflow signal (T1UDF)
PWM signal (PWMOUT)
CNTR0 output signal selection bit
Timer 2 control bit
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
Timer control register W2
at RAM back-up : state retained
at reset : 00002
W23
W22
W21
W20
W11
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
XIN input
CNTR0 input
Timer 1 count auto-stop circuit selection
bit
Timer 1 control bit
Timer 1 count source selection bits
0
1
0
1
W10
0
1
0
1
Timer control register W1
R/W
TAW1/TW1A
at RAM back-up : state retained
at reset : 00002
W13
W12
W11
W10
R/W
TAW2/TW2A
W31
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Timer 3 count auto-stop circuit selection
bit (Note 2)
Timer 3 control bit
Timer 3 count source selection bits
0
1
0
1
W30
0
1
0
1
Timer control register W3
at RAM back-up : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW3/TW3A
0
1
Stop (state initialized)
Operating
Prescaler control bit
Timer control register PA
W
TPAA
at RAM back-up : 02
at reset : 02
PA0
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