AT49BV8011(T)/8004(T)
2
Description
The AT49BV80XX(T) is a 2.7- to 3.6-volt 8-megabit Flash
memory organized as 524,288 words of 16 bits each or
1,048,576 bytes of 8 bits each. The x16 data appears on
I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The mem-
ory is divided into 24 sectors – AT49BV8004(T) or 22
sectors – AT49BV8011(T) for erase operations. The device
is offered in 48-pin TSOP and 48-ball CBGA packages.
The device has CE, and OE control signals to avoid any
bus contention. This device can be read or reprogrammed
using a single 2.7V power supply, making it ideally suited
for in-system programming.
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and V
CC.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
A VPP pin is provided to improve program/erase times.
This pin can be tied to V
CC. To take advantage of faster
programming and erasing, the pin should supply 4.5 to 5.5
volts during program and erase operations.
A six byte command (bypass unlock) sequence to remove
the requirement of entering the three byte program
sequence is offered to further improve programming time.
After entering the six byte code, only single pulses on the
write control lines are required for writing into the device.
This mode (single pulse byte/word program) is exited by
powering down the device, or by pulsing the RESET pin
low for a minimum of 50 ns and then bringing it back to V
CC.
Erase and Erase Suspend/Resume commands will not
work while in this mode; if entered they will result in data
being programmed into the device. It is not recommended
that the six byte code reside in the software of the final
product but only exist in external programming code.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
set at logic “1”, the device is in word configuration, I/O0-
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0-I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8-I/O14 are
tri-stated, and the I/O15 pin is used as an input for the LSB
(A-1) address function.
CBGA Top View
A
B
C
D
E
F
1
234567
VSS
I/O1
I/O3
I/O4
I/O6
VSS
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
CE
I/O8
I/O10
I/O12
I/O14
BYTE
A0
I/O0
I/O2
I/O5
I/O7
A16
A1
A5
NC
A11
A15
A2
A6
A18
NC
A10
A14
A4
A17
NC
RESET
A8
A12
A3
A7
RDY/BUSY
WE
A9
A13
8
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
WE
RESET
VPP
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0