參數(shù)資料
型號: AT89LP51-20MU
廠商: Atmel
文件頁數(shù): 90/117頁
文件大?。?/td> 0K
描述: MCU 8051 4K FLASH 20MHZ 7X7MLF
標準包裝: 360
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 托盤
74
3709D–MICRO–12/11
AT89LP51/52
MOV WDTRST, #05Ah
MOV WDTRST, #0A5h
Note:
1. WDTCON.4 and WDTCON.3 function as WDIDLE and DISRTO only in Fast mode. In Compatibility mode these bits are in
Table 15-2.
WDTCON – Watchdog Control Register
WDTCON Address = A7H
Reset Value = 0000 0XX0B
Not Bit Addressable
PS2PS1PS0
WDIDLE(1)
DISRTO(1)
SWRST
WDTOVF
WDTEN
Bit
7
654
321
0
Symbol
Function
PS2
PS1
PS0
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
WDIDLE
WDT Disable during Idle(1). When WDIDLE = 0 the WDT continues to count in Idle mode. When WDIDLE = 1 the WDT
halts counting in Idle mode.
DISRTO
Disable Reset Output(1). When DISTRO = 0 the reset pin is driven to the same level as POL when the WDT resets.
When DISRTO = 1 the reset pin is input only.
SWRST
Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set
when an incorrect sequence is written to WDTRST. Must be cleared by software.
WDTOVF
Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect
sequence is written to WDTRST. Must be cleared by software.
WDTEN
Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The
WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST
Table 15-3.
WDTRST – Watchdog Reset Register
WDTCON Address = A6H
(Write-Only)
Not Bit Addressable
–––
––
Bit
7
654
321
0
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading
the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to
WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST.
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