參數(shù)資料
型號(hào): AT90USB647-AU
廠商: Atmel
文件頁(yè)數(shù): 24/106頁(yè)
文件大?。?/td> 0K
描述: IC AVR MCU 64K 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 450
系列: AVR®
應(yīng)用: USB 微控制器
核心處理器: AVR
程序存儲(chǔ)器類(lèi)型: 閃存(64 kB)
控制器系列: AT90 USB
RAM 容量: 4K x 8
接口: 2 線串行,SPI 串行,USART,USB
輸入/輸出數(shù): 48
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-TQFP,64-VQFP
包裝: 托盤(pán)
供應(yīng)商設(shè)備封裝: 64-TQFP
配用: ATSTK600-RC17-ND - STK600 ROUTING CARD AVR
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB647-16AU
AT90USB647-16AU-ND
24
7593L–AVR–09/12
AT90USB64/128
Figure 6-3.
On-chip data SRAM access cycles.
6.3
EEPROM data memory
The Atmel AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as
a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 373, page 377, and page 362 respectively.
6.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 6-3. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM corruption” on page 29. for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute address
Read
Wr
ite
CPU
Memory access instruction
Next instruction
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