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30
2543L–AVR–08/10
ATtiny2313
Power
Management
and Sleep
Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register select
which sleep mode (Idle, Power-down, or Standby) will be activated by the SLEEP instruction.
See
Table 13 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode,
the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, exe-
cutes the interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
tion. The figure is helpful in selecting an appropriate sleep mode.
MCU Control Register
– MCUCR
The Sleep Mode Control Register contains control bits for power management.
Bits 6, 4 – SM1..0: Sleep Mode Select Bits 1 and 0
These bits select between the five available sleep modes as shown in
Table 13.Note:
1. Standby mode is only recommended for use with external crystals or resonators.
Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the UART, Analog Comparator, ADC, USI, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and UART Transmit Complete interrupts. If wake-up from the Ana-
log Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode.
Bit
765
4321
0
PUD
SM1
SE
SM0
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
000
0000
0
Table 13. Sleep Mode Select
SM1
SM0
Sleep Mode
00
Idle
0
1
Power-down
1
0
Standby
1
Power-down