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參數(shù)資料
| 型號： | BT864AKPF |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 顏色編碼器電路 |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | BT864AKPF |
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Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.5 Video Timing
100138B
Conexant
1-15
1.5.1 Reset
If the RESET* pin is held low during a single rising edge of CLK, the subcarrier
phase is set to zero, and the horizontal and vertical counters are held to the first
pixel and second line of FIELD1. Counting resumes on the first rising edge of
CLK after rising RESET*.
A software reset will occur immediately after writing a 1 to register SRESET.
This will reset all software-programmable register bits to zero.
On power-up, the Bt864A/865A will automatically perform a timing and
software reset. The power-up state has the following configuration: interlaced,
NTSC CCIR601 black burst (no active video), and zero chroma scaling. Setting
register EACTIVE will enable active video. On power-up, the DACs are disabled
for 8 fields or until register 0x67 (0xCE as 8-bit address) is written.
1.5.2 Sync and Burst Timing
Table 1-2
lists the resolutions and clock rates for the various modes of operation.
Table 1-3
lists the horizontal counter values for the end of horizontal sync,
start of color burst, end of color burst, and the first active pixel for the various
modes of operation. The front porch is the interval before the next expected
falling HSYNC* when outputs are automatically blanked.
The horizontal sync width is measured between the 50% points of the falling
and rising edges of horizontal sync.
The start of color burst is measured between the 50% point of the falling edge
of horizontal sync and the first 50% point of the color burst amplitude (nominally
+20 IRE for NTSC/PAL
–
M and 150 mV for PAL
–
B, D, G, H, I, N, Nc above the
blanking level).
The end of color burst is measured between the 50% point of the falling edge
of horizontal sync and the last 50% point of the color burst envelope (nominally
+20 IRE for NTSC/PAL
–
M and 150 mV for PAL
–
B, D, G, H, I, N, Nc above the
blanking level).
Table 1-2. Field Resolutions and Clock Rates for Various Modes of Operation
Operating Mode
Active Luminance Resolution
(pixels)
Total Resolution (pixels)
Luminance
Pixel
Frequency
(MHz)
Horizontal
Vertical
Horizontal
Vertical
Porch = 0
Non
Interlaced
Field
Interlaced
Frame
Non
Interlaced
Interlaced
NTSC/PAL
–
M CCIR601
PAL
–
B, D, G, H, I, N, Nc
CCIR601
NTSC/PAL
–
M Square Pixel
PAL
–
B, D, G, H, I, N, Nc Square
Pixel
711
702
647
767
241
287
241
287
482
575
482
575
858 ± 1
864 ± 1
780 ± 1
944 ± 1
262 ± 1/4
312 ± 1/4
262 ± 1/4
312 ± 1/4
262.5 ± 1/4
312.5 ± 1/4
262.5 ± 1/4
312.5 ± 1/4
13.5000
13.5000
12.2727
14.7500
NOTE(S):
1. Tolerances apply to slave mode. Cumulative errors over color frame interval may result in subcarrier glitches.
2. Due to upsampling filter response, pixels near the boundary of the active definition will be reduced in amplitude due to
averaging with the blank level.
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| BT865AKPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
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