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參數(shù)資料
| 型號： | BT864AKPF |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 顏色編碼器電路 |
| 文件頁數(shù)： | 27/76頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | BT864AKPF |
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Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.5 Video Timing
100138B
Conexant
1-17
1.5.4 Slave Mode
The horizontal counter is incremented on every other rising edge of CLK. A
falling edge of HSYNC* resets it to one, indicating the start of a new line.
The vertical counter is incremented on the falling edge of HSYNC*. A falling
edge of VSYNC* resets it to one, indicating the start of a new field (interlaced
operation) or frame (noninterlaced operation).
A falling edge of VSYNC* that occurs within
±
1/4 of a scan line from the
falling edge of HSYNC* indicates the beginning of FIELD 1. A falling edge of
VSYNC* that occurs within
±
1/4 scan line from the center of the line indicates
the beginning of FIELD 2. Referring to
Figures 1-4
–
1-12
, start of VSYNC*
occurs on the falling HSYNC* at the beginning of the next expected FIELD 1 and
halfway between expected falling HSYNC* edges at the beginning of the next
expected FIELD 2.
HSYNC* and VSYNC* must remain low for at least 2 CLK cycles. The
operating mode (NTSC/PAL, interlaced/noninterlaced, square pixel/CCIR601,
and setup) is automatically determined when configured as a slave when the
SETMODE bit is zero. 525-line operation is assumed, unless 625-line operation
is detected by the number of lines in a field. Interlaced operation is detected by
observing the sequence of FIELD 1 or FIELD 2; if the field timing (odd follows
odd, even follows even) is repeated, then noninterlaced mode is assumed. The
frequency of operation (square pixels or CCIR) is detected by counting the
number of clocks per line. The pixel rate is assumed to be 13.5 MHz unless the
exact horizontal count for square pixels, ±1 count, is detected in between two
successive falling edges of HSYNC*.
NOTE:
Square pixel 625-line operation with this sequence requires one frame to
stabilize.
By setting SETMODE = 1, the video format control register bits (VIDFORM
[3:0], SETUPDIS, NONINTL, and SQUARE) will determine the operating mode.
1.5.5 FIELD Output
The FIELD output indicates whether FIELD 1 (logical zero) or FIELD 2 (logical
one) is being generated. This corresponds directly to the
“
bottom/top
”
convention
of some MPEG decoders. Field changes occur one CLK cycle after the falling
edge of VSYNC*. FIELD is output following the rising edge of CLK. Unless
special HSYNC* timing is programmed, FIELD output transitions low four CLK
periods following the falling edge of HSYNC* at the beginning of FIELD 1.
To invert the sense of the FIELD output, set the FIELDI bit to a logical one.
1.5.6 Pixel Blanking
BLANK* is registered on the rising edge of CLK. For video outputs, BLANK* is
pipelined to match the luminance and chrominance paths and is applied to the
digital video before analog conversion. The automatic horizontal blanking
sequence described in
Table 1-3
takes precedence over the BLANK* input.
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| BT865AKPF | Color Encoder Circuit |
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| BT867KPJ | Color Encoder Circuit |
| BT8920EPJ | Analog-to-Digital Converter， 16-Bit |
| BT8920EPJ600 | Analog-to-Digital Converter， 16-Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BT864AKRF | 制造商:CONEXANT 制造商全稱:CONEXANT 功能描述:YCrCb to NTSC/PAL Digital Video Encoder |
| BT864KPF | 制造商:BT 功能描述:COLOR SIGNAL ENCODER, PQFP52 |
| BT864KPF-ES1 | 制造商:BT 功能描述:864KPF-ES1 |
| BT865A | 制造商:CONEXANT 制造商全稱:CONEXANT 功能描述:High Performance YCrCb to NTSC/PAL Digital Video Encoders |
| BT865AKPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
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