INTRODUCTION
The BU-61743/61745 RT, and BU-61843/61845/61864/61865
BC/RT/MT Enhanced Mini-ACE family of MIL-STD-1553 termi-
nals comprise a complete integrated interface between a host
processor and a MIL-STD-1553 bus. All members of the
Enhanced Mini-ACE family are packaged in the same 1.0 square
inch flatpack package. The Enhanced Mini-ACE hybrids are
nearly 100% footprint and software compatible with the previous
generation Mini-ACE and Mini-ACE Plus terminals, and are soft-
ware compatibility with the original ACE series.
The Enhanced Mini-ACE provides complete multiprotocol sup-
port of MIL-STD-1553A/B/McAir and STANAG 3838. All versions
integrate dual transceiver; along with protocol, host interface,
memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The Enhanced Mini-ACEs include a 5V, voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 and McAir compatibility. As a means of reducing
power consumption, there are versions for which the logic is
powered by 3.3V, rather than 5V. To provide further flexibility, the
Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or
20 MHz clock inputs.
One of the new salient features of the Enhanced Mini-ACE is its
Enhanced bus controller architecture. The Enhanced BC's high-
ly autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE RT offers the same choices of single,
double, and circular buffering for individual subaddresses as
ACE and Mini-ACE (Plus). New enhancements to the RT archi-
tecture include a global circular buffering option for multiple (or
all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt
events, and an option to automatically initialize to RT mode with
the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE's Monitor architecture.
To minimize board space and "glue" logic, the Enhanced Mini-
ACE terminals provide the same wide choice of host interface
configurations as the ACE and Mini-ACE (Plus). This includes
support of interfaces to 16-bit or 8-bit processors, memory or
port type interfaces, and multiplexed or non-multiplexed
address/data buses. In addition, with respect to ACE/Mini-ACE
(Plus), the worst case processor wait time has been significant-
ly reduced. For example, assuming a 16 MHz clock, this time has
been reduced from 2.8
s to 632 ns for read accesses, and to
570 ns for write accesses.
The Enhanced Mini-ACE series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL-PRF-38534C, the terminals are ideal for military and
industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the Enhanced Mini-ACE series terminals are
fully monolithic, requiring only a +5 volt power input. The trans-
mitters are voltage sources, which provide improved line driving
capability over current sources. This serves to improve perfor-
mance on long buses with many taps. The transmitters also offer
an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +5V-only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15 volt or 12 volt transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This characteristic allows for longer cable lengths
between a system connector and the isolation transformers of an
embedded 1553 terminal.
To provide compatibility to McAir specs, the Enhanced Mini-
ACEs are available with an option for transmitters with increased
rise and fall times.
Additionally, for MIL-STD-1760 applications, the Enhanced Mini-
ACE provides an option for a minimum stub voltage level of 20
volts peak-to-peak, transformer coupled.
The receiver sections of the Enhanced Mini-ACE are fully com-
pliant with MIL-STD-1553B Notice 2 in terms of front end over-
voltage protection, threshold, common mode rejection, and word
error rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Enhanced Mini-ACE to the host
processor consists of 24 internal operational registers for normal
operation, an additional 24 test registers, plus 64K words of
shared memory address space. The Enhanced Mini-ACE's 4K X
16 or 64K X 17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
4