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參數(shù)資料
| 型號： | BU-61845G4-132K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| 封裝： | GULL WING, PACKAGE-72 |
| 文件頁數(shù)： | 40/56頁 |
| 文件大?。?/td> | 321K |
| 代理商： | BU-61845G4-132K |
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Data Transfer Acknowledge or Polarity Select. In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR
should be asserted high (logic "1") for a read operation and low (logic "0") for a write operation. In 16-bit buffered
mode, if POL_SEL is connected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and high
(logic "1") for a write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = “0" and 16/8 = "0"), POL_SEL input signal used to control the
logic sense of the MSB/LSB signal. If POL_SEL is connected to logic “0", MSB/LSB should be asserted low (logic "0")
to indicate the transfer of the least significant byte and high (logic "1") to indicate the transfer of the most significant
byte. If POL_SEL is connected to logic “1", MSB/LSB should be asserted high (logic "1") to indicate the transfer of the
least significant byte and low (logic "0") to indicate the transfer of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM interface bus
in response to a data transfer grant (DTGRT). The Enhanced Mini-ACE's RAM transfers over A15-A0 and D15-D0 will
be framed by the time that DTACK is asserted low.
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred (MSB or LSB).
The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indicate that control
of the external processor/RAM bus has been transferred from the host processor to the Enhanced Mini-ACE.
Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to select between the 16 bit data
transfer mode (16/8= "1") and the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the processor/RAM
interface bus (address and data buses).
Memory Write or Zero Wait . In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode
(ZEROWAIT = “0") and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to strobe data into
external RAM (normally connected to the WR input signal on external RAM chips).
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG, and MSB/LSB
(for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is, the Enhanced Mini-ACE's
internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/LSB when ADDR_LAT is
high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be hardwired to
logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT should be connected to a signal
that indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles (normally con-
nected to the OE input signal on external RAM chips).
Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer cycle between the host proces-
sor and the ENHANCED MINI-ACE. STRBD must be asserted low through the full duration of the transfer cycle.
Read/Write. For a host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if
POL_SEL is logic "0, then RD/WR should be low (logic “0") for read accesses and high (logic "1") for write accesses. If
POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered mode, then RD/WR is high
(logic "1") for read accesses and low (logic "0") for write accesses.
Generally connected to a CPU address decoder output to select the Enhanced Mini-ACE for a transfer to/from either
RAM or register.
DESCRIPTION
PROCESSOR INTERFACE CONTROL
POL_SEL (1) /
DTACK (0)
MSB / LSB (1) /
DTGRT (1)
16 / 8 (1) /
DTREQ (0)
ZEROWAIT (1) /
MEMWR (0)
ADDR_LAT(1) /
MEMOE (0)
STRBD (1)
RD / WR
SELECT (1)
SIGNAL NAME
29
64
24
23
14
62
63
61
PIN
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