參數(shù)資料
型號(hào): BU-62843
英文描述: MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述: 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇?
文件頁數(shù): 50/56頁
文件大?。?/td> 368K
代理商: BU-62843
50
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
C/BE[3]# (I)
32
Bus Command and Byte Enables.These signals are multiplexed on the same pins.
During the address phase of a bus operation, these pins identify the bus command, as
shown in the table below. During the data phase of a bus operation, these pins are
used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte
3 (MSB).The PACE responds to the following PCI commands:
C/BE[3:0]#
DESCRIPTION (DURING ADDRESS PHASE)
0
1
1
0
Memory Read
0
1
1
1
Memory Write
1
0
1
0
Configuration Read
1
0
1
1
Configuration Write
1
1
0
0
Memory Read Multiple
1
1
1
0
Memory Read Line
1
1
1
1
Memory Write and Invalidate
Note that the last three memory commands are aliased to the basic memory com-
mands: Memory Read and Memory Write.
C/BE[2]# (I)
43
C/BE[1]# (I)
52
C/BE[0]# (I)
61
PAR (I/O)
51
Clock input.The rising edge of this signal is the reference upon which all other clock signals
are based, with the exception of RST# and INTA#.The maximum frequency accepted is 33
MHz and the minimum is 0 Hz.
PCI_CLK (I)
30
Parity.This signal is even parity across the entire AD[31:0] field along with the
C/BE[3:0]# field.The parity is stable in the clock following the address phase and is
sourced by the Bus Master. During the data phase for write operations, the Bus Master
sources this signal on the clock following IRDY# active. During the data phase for read
operations, this signal is sourced by the Target and is valid on the clock following
TRDY# active.The PAR signal therefore has the same timing as AD[31:0], delayed by
one clock.
TABLE 71. PCI BUS ADDRESS AND DATA SIGNALS (CONTINUED)
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
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