參數(shù)資料
型號(hào)： BU-62843
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 9/56頁(yè)
文件大?。?/td> 368K
代理商： BU-62843
9
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
FAIL-SAFE MODE
Fail-safe Errors occur when the internal ACE fails to assert it's
hand-shake signal within 1 millisecond (programmable) of when
the internal Strobe or Request signal is asserted. Four possible
FAIL-SAFE Modes determine how this situation is handled:
MODE 1 - FAIL-SAFE OFF
PCI Enhanced Mini-ACE will wait indefinitely for the transaction
to complete.The local bus could hang as a result.The FAILSAFE
ERROR bit and interrupt will not be generated even if the enable
bit is set.
MODE 2 - FAIL-SAFE RETRY
PCI Enhanced Mini-ACE will retry the transfer on the local bus
when the FAIL-SAFE timer times out.
MODE 3 - FAIL-SAFE HALT
Once the FAIL-SAFE timer times out, all future transfers will be
terminated with a target abort until the PCI master clears the
interrupt.
MODE 4 - FAIL-SAFE SKIP
Once the FAIL-SAFE timer times out, the current transaction is
discarded or skipped and the next transaction, whether a stored
write in the FIFO or a new transaction, will be attempted.
0
0
0
1
1
0
1
1
TABLE 11. FAIL-SAFE MODE
BIT 16
BIT 17
Fail-safe Off
Fail-safe Retry
Fail-safe Halt
Fail-safe Skip
FAIL-SAFE MODE
NOTE: Fail-safe errors are extremely unlikely.
31 (MSB)
0
TABLE 12. REG2 FAIL-SAFE TIMER REGISTER
(READ 808H)
BIT
DESCRIPTION
16
0
15
FAIL-SAFE TIMER COUNT - BIT 15 (MSB)
0 (LSB)
FAIL-SAFE TIMER COUNT - BIT 0 (LSB)
FAIL-SAFE TIMER COUNT
Read this register to obtain the current value of the fail-safe
timer. Default is 8400h.
31 (MSB)
16
15
0 (LSB)
0
0
FAIL-SAFE TIMER VALUE - BIT 15 (MSB)
FAIL-SAFE TIMER VALUE - BIT 0 (LSB)
TABLE 13. REG3 FAIL-SAFE TIMER PRELOAD
REGISTER (READ/WRITE 80CH)
BIT
DESCRIPTION
FAIL-SAFE TIMER VALUE
Write to this register to set the value for the fail-safe timer.The
default value is 8400h and no access to this register is needed
for normal applications.
31 (MSB)
16
15
0 (LSB)
0
0
DISCARD TIMER CURRENT - BIT 15 (MSB)
DISCARD TIMER CURRENT - BIT 0 (LSB)
TABLE 14. REG4 DISCARD TIMER REGISTER
(READ 810H)
BIT
DESCRIPTION
DISCARD TIMER CURRENT
Read this register to obtain the current value of the DISCARD
TIMER. Default is 0000h.
31 (MSB)
16
15
0 (LSB)
0
0
DISCARD TIMER VALUE - BIT 15 (MSB)
DISCARD TIMER VALUE - BIT 0 (LSB)
TABLE 15. REG5 DISCARD TIMER PRELOAD
REGISTER (READ/WRITE 814H)
BIT
DESCRIPTION
DISCARD TIMER VALUE
Write this register to set the value to be used for the discard
timer.The default value is "0".The default value meets the PCI
spec and no access to this register is needed for normal appli-
cations.
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