- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄210366 > BX80532KC1900E (INTEL CORP) 1900 MHz, MICROPROCESSOR PDF資料下載
參數(shù)資料
| 型號： | BX80532KC1900E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1900 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 108/132頁 |
| 文件大?。?/td> | 2316K |
| 代理商： | BX80532KC1900E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁當前第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁
Intel Xeon Processor MP with up to 2MB L3 Cache
6-3
Features
BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted
at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If
the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will
return to Normal state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should
only be deasserted one or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
6.2.4
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor will stay in this state until the snoop on the system bus has been
serviced (whether by the processor or another agent on the system bus). After the snoop is serviced,
the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
6.2.5
Sleep State—State 5
The Sleep state is a very low power state in which each processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing
the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT
states.
Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event
occurs. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. For
Intel Xeon processor MP on the 0.13 micron process processors, the SLP# pin may only be
asserted when all logical processors are in the Stop-Grant state. SLP# assertions while the
processors are not in the Stop-Grant state is out of specification and may result in illegal operation.
相關PDF資料 |
PDF描述 |
|---|---|
| BU-61582D0-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D0-300K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-410S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-431 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2000E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2200DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.2GHZ 603-PIN IN - Boxed Product (Development Kits) |
| BX80532KC2400D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KC2400DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
發(fā)布緊急采購，3分鐘左右您將得到回復。