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| 型號(hào)： | BX80532KC1900E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1900 MHz, MICROPROCESSOR |
| 文件頁(yè)數(shù)： | 30/132頁(yè) |
| 文件大小： | 2316K |
| 代理商： | BX80532KC1900E |
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Intel Xeon Processor MP with up to 2MB L3 Cache
9-27
NOTES:
1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate
BR2# and BR3# to the processor VCC..
§
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level where permanent silicon damage may occur.
Measurement of the temperature is accomplished through an internal thermal
sensor which is configured to trip at approximately 135°C. Upon assertion of
THERMTRIP#, the processor will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (Vcc) must be removed following the assertion of
sequence and timing requirements.
Once activated, THERMTRIP# remains latched until RESET# is asserted. While
the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor’s
junction temperature remains at or above the trip level, THERMTRIP# will again be
asserted.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TRDY#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. See the appropriate platform design guideline for
additional information.
VCCA
I
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to
provide clean power to the PLL. The tolerance and total ESR for the filter is
important. Refer to the appropriate platform design guidelines for complete
implementation details.
VCCIOPLL
I
VCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow the
guidelines for VCCA (Section 2.5). Refer to the appropriate platform design
guidelines for complete implementation details.
VCCSENSE
VSSSENSE
O
The Vccsense and Vsssense pins are the points for which processor minimum and
maximum voltage requirements are specified. Uniprocessor designs may utilize
these pins for voltage sensing for the processor's voltage regulator. However, multi-
processor designs must not connect these pins to sense logic, but rather utilize
them for power delivery validation
.
VID[4:0]
O
VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages (VCC). Unlike previous generations of processors, these are logic
signals and are driven by the Intel Xeon processor MP on the 0.13 micron process
processor. Hence the voltage supply for these pins (SM_Vcc) must be valid before
the VRM supplying Vcc to the processor is enabled (see Figure ). Conversely, the
VRM output must be disabled prior to the voltage supply for these pins becomes
invalid. The VID pins are needed to support processor voltage specification
variations. See Table 4 for definitions of these pins. The power supply must supply
the voltage that is requested by these pins, or disable itself.
VSSA
I
VSSA provides an isolated, internal ground for internal PLL’s. Do not connect
directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a
appropriate platform design guidelines for complete implementation details.
Table 52. Signal Definitions (Sheet 9 of 9)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61582D0-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D0-300K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-410S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-431 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2000E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KC2200DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.2GHZ 603-PIN IN - Boxed Product (Development Kits) |
| BX80532KC2400D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KC2400DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
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