參數(shù)資料
型號: BX80532KC1900E
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 1900 MHz, MICROPROCESSOR
文件頁數(shù): 35/132頁
文件大?。?/td> 2316K
代理商: BX80532KC1900E
Intel Xeon Processor MP with up to 2MB L3 Cache
1-3
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“System bus” refers to the interface between the processor, system core logic (the chipset
components), and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O. For this document, “system bus” is used as the generic term for the “Intel
Xeon processor MP with up to 2-MB L3 cache processor system bus”.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
603-Pin Socket - The connector which mates the Intel Xeon processor MP with up to 2-MB
L3 Cache in INT-mPGA package to the baseboard. The 603-pin socket is a surface mount
technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment to the
platform. See the 603-Pin Socket Design Guidelines for details regarding this socket.
604-Pin Socket - The 604-pin socket contains an additional contact to accept the additional
keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The
604-pin socket will also accept processors with the INT-mPGA package. Since the additional
contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this
location. Therefore, the additional keying pin will not require a baseboard via nor a surface-
mount pad.
Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using “flip chip” design,
where the processor is attached to the substrate face-down for better signal integrity, more
efficient heat removal and lower inductance.
FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin
Grid Array substrate with an integrated heat spreader (IHS).
Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the Intel Xeon processor MP with up to 2-MB L3 cache processor. The IHS will
come in two sizes for the Intel Xeon processor MP with up to 2-MB L3 cache processor, see
Section 4 for specific details.
Interposer - The structure on which the processor core package and I/O pins are mounted.
INT-mPGA - Packaging technology with the processor die on a Flip Chip Ball Grid Array
(FC-BGA) core mounted to a pinned interposer with an integrated heat spreader (IHS).
OEM - Original Equipment Manufacturer.
Processor core - The processor’s execution engine. All AC timing and signal integrity
specifications are to the pads of the processor core.
Processor Information ROM (PIROM) - A memory device located on the Intel Xeon
processor MP with up to 2-MB L3 cache processor and the Intel Xeon processor in INT-
mPGA package, accessible via the SMBus which contains information regarding the
processor’s features. This device is shared with a scratch EEPROM. The PIROM is
programmed during the manufacturing and is write-protected. See Section 6.4 for details on
the PIROM.
相關(guān)PDF資料
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BU-61582D0-290S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
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BU-61582D1-391Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-61582D1-410S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
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