參數(shù)資料
型號: C8051F019R
廠商: Silicon Laboratories Inc
文件頁數(shù): 63/154頁
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 48TQFP
標準包裝: 1
系列: C8051F018
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1049-1
C8051F018
C8051F019
1.7.
Analog to Digital Converter
The C8051F018/9 have an on-chip 10-bit SAR ADC with a 9-channel input multiplexer.
With a maximum
throughput of 100ksps, the ADC offers true 10-bit accuracy with an INL of
1LSB. The ADC has a maximum
throughput of 100ksps. There is also an on-board 15ppm voltage reference, or an external reference may be used
via the VREF pin.
The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel
is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the
eight external input channels can be configured as either two single-ended inputs or a single differential input. The
system controller can also put the ADC into shutdown to save power.
Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or
an external signal input. This flexibility allows the start of conversion to be triggered by software events, external
HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in
software to determine the end of conversion.
The resulting 10-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a
specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the
controller unless the converted data is within the specified window.
Figure 1.9. ADC Diagram
100ksps
SAR
ADC
Control & Data
SFR's
SFR Bus
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
+
-
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
TEMP
SENSOR
VREF
REF
Rev. 1.2
16
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