參數(shù)資料
型號: C8051F019R
廠商: Silicon Laboratories Inc
文件頁數(shù): 80/154頁
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 48TQFP
標準包裝: 1
系列: C8051F018
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1049-1
C8051F018
C8051F019
Figure 5.7. ADC0CN: ADC Control Register
R/W
Reset Value
ADCEN
ADCTM
ADCINT
ADBUSY
ADSTM1
ADSTM0
ADWINT
ADLJST
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xE8
Bit7:
ADCEN: ADC Enable Bit
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
Bit6:
ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is always done unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
ADSTM1-0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks
10: ADC tracks only when CNVSTR input is logic low
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
Bit5:
ADCINT: ADC Conversion Complete Interrupt Flag
(Must be cleared by software)
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
Bit4:
ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1-0 = 00b
Bits3-2: ADSTM1-0: ADC Start of Conversion Mode Bits
00: ADC conversion started upon every write of 1 to ADBUSY
01: ADC conversions taken on every overflow of Timer 3
10: ADC conversion started upon every rising edge of CNVSTR
11: ADC conversions taken on every overflow of Timer 2
Bit1:
ADWINT: ADC Window Compare Interrupt Flag
(Must be cleared by software)
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
Bit0:
ADLJST: ADC Left Justify Data Bit
0: Data in ADC0H:ADC0L Registers is right justified
1: Data in ADC0H:ADC0L Registers is left justified
31
Rev. 1.2
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