參數(shù)資料
型號: C8051F230R
廠商: Silicon Laboratories Inc
文件頁數(shù): 117/146頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1011-1
C8051F2xx
72
Rev. 1.6
SFR Definition 9.4. PSW: Program Status Word
Bit7:
CY: Carry Flag.
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
Bit6:
AC: Auxiliary Carry Flag.
This bit is set when the last arithmetic operation results in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general-purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Note: Any instruction which changes the RS1–RS0 bits must not be immediately followed by
the “MOV Rn, A” instruction.
Bit2:
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1:
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0:
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
R/W
R
Reset Value
CY
AC
F0
RS1
RS0
OV
F1
PARITY
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit
addressable)
0xD0
RS1
RS0
Register Bank
Address
0
0x00–0x07
0
1
0x08–0x0F
1
0
2
0x10–0x17
1
3
0x18–0x1F
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