參數(shù)資料
型號: C8051F230R
廠商: Silicon Laboratories Inc
文件頁數(shù): 121/146頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標準包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1011-1
C8051F2xx
76
Rev. 1.6
9.4.4. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP–EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate.
9.4.5. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. NOTE: If a
Flash write or erase is performed, the MCU is stalled during the operation and interrupts will not be ser-
viced until the operation is complete. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and fol-
lowing instruction.
ADC0 End of Conversion
0x007B
15
ADCINT (ADC0CN.5)
EADC0 (EIE2.1)
Software Controlled Interrupt 0
0x0083
16
SCI0 (SWCINT.4)
ESCI0 (EIE2.2)
Software Controlled Interrupt 1
0x008B
17
SCI1 (SWCINT.5)
ESCI1 (EIE2.3)
Software Controlled Interrupt 2
0x0093
18
SCI2 (SWCINT.6)
ESCI2 (EIE2.4)
Software Controlled Interrupt 3
0x009B
19
SCI3 (SWCINT.7)
ESCI3 (EIE2.5)
Unused Interrupt Location
0x00A3
20
None
Reserved (EIE2.6)
External Crystal OSC Ready
0x00AB
21
XTLVLD (OSCXCN.7)
EXVLD (EIE2.7)
Table 9.4. Interrupt Summary (Continued)
Interrupt Source
Interrupt
Vector
Priority
Order
Interrupt-Pending Flag
Enable
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