參數(shù)資料
型號: C8051F230R
廠商: Silicon Laboratories Inc
文件頁數(shù): 45/146頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標準包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1011-1
C8051F2xx
Rev. 1.6
139
18. JTAG
Description
The MCU has an on-chip JTAG interface and logic to support Flash read and write operations and non-
intrusive in-circuit debug. The C8051F2xx may be placed in a JTAG test chain in order to maintain only
one JTAG interface in a system for boundary scan of other parts, and still utilize the C8051F2xx debug and
Flash programming. However, the C8051F2xx does NOT support boundary scan and will act as BYPASS
as specified in IEEE 1149.1.
The JTAG interface is implemented via four dedicated pins on the MCU, which are TCK, TMS, TDI, and
TDO. These pins are all 5 volt tolerant.
Through the 16-bit JTAG Instruction Register (IR), five instructions shown in JTAG Register Definition 18.1
can be commanded. These commands can either select the device ID code, or select registers for Flash
programming operations. BYPASS is shown to illustrate its default setting. There are four Data Registers
associated with the Flash read and write operations on the MCU.
JTAG Register Definition 18.1. IR: JTAG Instruction
Reset Value
0x0000
Bit15
Bit0
IR value
Instruction
Description
0x0004
IDCODE
Selects device ID Register
0xFFFF
BYPASS
Selects bypass Data Register and is DEFAULT for the device. Note:
The device does NOT support boundary scan. However, it may be
placed in a scan chain and bypassed in a system of other devices utiliz-
ing boundary scan.
0x0082
Flash Control
Selects FLASHCON Register to control how the interface logic
responds to reads and writes to the FLASHDAT Register
0x0083
Flash Data
Selects FLASHDAT Register for reads and writes to the Flash memory
0x0084
Flash Address
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
0x0085
Flash Scale
Selects FLASHSCL Register which controls the prescaler used to gen-
erate timing signals for Flash operations
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