CIP-51TM Micro" />
參數(shù)資料
型號: C8051F230R
廠商: Silicon Laboratories Inc
文件頁數(shù): 54/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1011-1
C8051F2xx
Rev. 1.6
15
Figure 1.4. C8051F231 Block Diagram (32 LQFP)
1.1.
CIP-51TM Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Silcon Labs’ proprietary CIP-51 microcon-
troller core.
The CIP-51 is fully compatible with the MCS-51TM instruction set.
Standard 803x/805x
assemblers and compilers can be used to develop software. The core contains the peripherals included
with a standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM,
an optional 1024 bytes of XRAM, 128 byte Special Function Register (SFR) address space, and four byte-
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes
70% of its instructions in one or two system clock cycles, with only four instructions taking more than four
system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to
execute them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
8kbyte
FLASH
256 byte
SRAM
VDD
Monitor,
WDT
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timer 0
Timer 1
Timer 2
CP0
CP1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
P
1
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P
0
D
r
v
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P
2
D
r
v
CP0+
CP0-
CP1+
CP1-
P
0
M
U
X
Port I/O Mode
& Config.
Port Mux
Control
Comparator
Config.
VDD
GND
Reset
/RST
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Internal
Oscillator
Clock & Reset
Configuration
Digital Power
Emulation HW
P
1
M
U
X
CP0
CP1
P
2
M
U
X
SPI
NC
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