Rev. 1.4
59
C8051F93x-C8051F92x
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
RST Output Low Voltage
IOL = 1.4 mA,
——
0.6
V
RST Input High Voltage
VDD = 2.0 to 3.6 V
VDD – 0.6 ——
V
VDD = 0.9 to 2.0 V
0.7 x VDD ——
V
RST Input Low Voltage
VDD = 2.0 to 3.6 V
——
0.6
V
VDD = 0.9 to 2.0 V
——
0.3 x VDD
V
RST Input Pullup Current
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
4
20
—
30
A
VDD/DC+ Monitor Thresh-
old (VRST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.7
1.85
1.75
1.9
1.8
V
VBAT Ramp Time for
Power On
One-cell Mode: VBAT Ramp 0–0.9 V
Two-cell Mode: VBAT Ramp 0–1.8 V
——
3
ms
VBAT Monitor Threshold
(VPOR)
Initial Power-On (VBAT Rising)
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
—
0.7
—
0.75
0.8
0.95
—
0.9
—
V
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650
1000
s
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
—
7
10
kHz
Reset Time Delay
Delay between release of any reset
source and code
execution at location 0x0000
—10—
s
Minimum RST Low Time to
Generate a System Reset
15
—
s
VDD Monitor Turn-on Time
—
300
—
ns
VDD Monitor Supply
Current
—7—
A