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| 型號(hào)： | C9530CT |
| 英文描述： | ST7262 - LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器|的CMOS | TSSOP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 180K |
| 代理商： | C9530CT |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07033 Rev. **
5/1/2000
Page 2 of 14
APPROVED PRODUCT
C9530
Pin Description
Pin No.
3
Pin Name
XIN
PWR
VDDA
I/O
I
Description
Crystal Buffer input pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can
Oscillator is used or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically 33.33
MHz
Output Enable for clock bank A. Causes the CLKA (0:4) output
clocks to be in a Tri-state condition when driven to a logic low level.
Output Enable for clock bank B. Causes the CLKB (0:4) output
clocks to be in a Tri-state condition when driven to a logic low level.
When this output signal is a logic low level, it indicates that the
output clocks of the A bank are locked to the input reference clock.
This output is latched.
When this output signal is at a logic low level, it indicates that the
output clocks of the B bank are locked to the input reference clock.
This output is latched.
Clock Bank A selection bits. These control the clock frequency that
will be present on the outputs of the A bank of buffers. See table on
page one for frequency codes and selection values.
Clock Bank B selection bits. These control the clock frequency that
will be present on the outputs of the B bank of buffers. See table on
page one for frequency codes and selection values.
SMBus address selection input pins. See SMBus Address table.
Enables Spread Spectrum clock modulation when at a logic low
level, see pg. 3.
Data for the internal SMBus circuitry. See pg 4.
Clock for the internal SMBus circuitry. See pg. 4
3.3V common power supply pin for Bank A PCI clocks CLKA (0:4).
3.3V common power supply pin for Bank B PCI clocks CLKB (0:4).
Power supply for internal Core logic.
Power for internal analog circuitry. This supply should have a
separately decoupled current source from VDD.
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x and 4x Xin clock).
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x, and 4x Xin clock).
Ground pins for the device
4
XOUT
VDDA
O
1
REF
VDD
O
24*
OEA
VDD
I
25*
OEB
VDD
I
18
AGOOD#
VDD
O
31
BGOOD#
VDD
O
6*, 7*
SA(0,1)
VDD
I
43*, 42*
SB(0,1)
VDD
I
20*, 21*, 22*
27*
IA(0:2)
SSCG#
VDD
VDD
I
I
48
47
SDATA
SCLK
VDDA
VDDB
VDD
AVDD
VDD
VDD
-
-
-
-
I/O
I
PWR
PWR
PWR
PWR
11, 14
38, 35
2, 44, 46
23, 29, 30
9, 10, 12,
15, 16
40, 39, 37,
34, 33
5, 8, 13, 17,
19, 26, 28,
32, 36, 41,
45
Notes
: Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no
external circuitry is connected to them.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic will be canceled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both
input and output functionality of the pin(s).
CLKA
(0:4)
CLKB
(0:4)
VSS
VDDA
O
VDDB
O
-
PWR
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| C9530CY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
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| C9531CY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|SSOP|28PIN|PLASTIC |
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