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參數(shù)資料
| 型號： | C9530CT |
| 英文描述： | ST7262 - LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器|的CMOS | TSSOP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 180K |
| 代理商： | C9530CT |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07033 Rev. **
5/1/2000
Page 6 of 14
APPROVED PRODUCT
C9530
Test Table
These output frequencies will be present when SMBus byte 0 bit 7 has been set to a logic 0 state.
Test Function
Clock
CLKA(0:4)
Frequency
XIN/6
Outputs
CLKB(0:4)
XIN/4
Table 3
REF
XIN
Notes:
1. XIN is the frequency of the clock that is present on the XIN input during test mode.
Byte 1: A Bank and REF Clock Control Register
(
1 = Enable, 0 = Stopped at a low level)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
1
16
15
12
10
9
Description
Reserved
Reserved
REF Enable/Stopped
CLKA4 Enable/Stopped
CLKA3 Enable/Stopped
CLKA2 Enable/Stopped
CLKA1 Enable/Stopped
CLKA0 Enable/Stopped
Byte 2: B Bank Clock Control Register
(1 = Enable, 0 = Stopped at a low level)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
-
33
34
37
39
40
Description
Reserved
Reserved
Reserved
CLKB4 Enable/Stopped
CLKB3 Enable/Stopped
CLKB2 Enable/Stopped
CLKB1 Enable/Stopped
CLKB0 Enable/Stopped
Note: Stopping a clock indicated that the clock output is fixed in a logic low state. This effect will occur within 2 clock
cycles from the time the bit is set and does so in a manner so as not to cause any short or runt clock cycles. When the
stop is bit is changed from a stopped state to a running state the same (maximum 2 clock latency) delay occurs with the
first cycle being full in period (for the frequency that is selected
Internal Crystal Oscillator
This device will operate in two input reference clock configurations. In its simplest mode a 33.33 MHz fundamental cut
parallel resonant crystal is attached to the XIN and XOUT pins.
In the second mode a 33.33MHz input reference clock is driven in on the XIN clock from an external source. In this
application the XOUT pin must be left disconnected.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of
these control signals is determined by the SMBus register Byte 0 Bit 0. At initial power up this bit is set of a logic 1 state
and thus the frequency selections are controlled by the logic levels present on the devices SA(0,1) and SB(0,1) pins. If
the application does not use an SMBus interface then hardware frequency selection SA(0,1), (SB(0,1) that must be
used. If it is desired to control the output clocks using an SMBus interface, then this bit (Byte 0 Bit 0) must first be set to
a low state. After this is done the device will use the contents of the internal SMBus register Byte 0, Bits 1,2,3 and 4) to
control the output clock’s frequency.
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| C9530CY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
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| C9531CY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|SSOP|28PIN|PLASTIC |
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