參數(shù)資料
型號(hào)： C9530CT
英文描述： ST7262 - LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI
中文描述： CPU系統(tǒng)時(shí)鐘發(fā)生器|的CMOS | TSSOP封裝| 48PIN |塑料
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 180K
代理商： C9530CT
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07033 Rev. **
5/1/2000
Page 9 of 14
APPROVED PRODUCT
C9530
AC Parameters
Symbol
Parameter
Output Frequency
100 MHz
Min
Max
9.5
10.5
Units
Notes
133 MHz
Min
7.0
66 MHz
Min
14.5
33 MHz
Min
25.5
Max
8.0
Max
15.5
Max
30.5
Tcyc
CLKA(0:4) CLKB(0:4)
period
CLKA(0:4) CLKB(0:4) period
CLKA(0:4) CLKB(0:4) low
time
CLKA(0:4) a, CLKB(0:4)rise
and fall times
(Any CLK ) to (Any CLK)
Skew time
CLK(A:B)(0:4) Cycle to
Cycle Jitter
REFOUT rise and fall times
REFOUT Cycle to Cycle
Jitter
OE to clock enable delay (all
outputs)
OE to clock disable delay (all
outputs)
All clock Stabilization from
power-up
This parameter is measured as an average over 1uS duration, with an input frequency of 33.333 MHz
All outputs loaded as per table 1 below.
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V (see Fig.6A and Fig.6B)
Probes are placed on the pins, and measurements are acquired at 1.5V. (See Figs.6A & 6B)
This measurement is applicable with Spread ON or OFF.
Probes are placed on the pins, and measurements are acquired at 2.4Vs, (see Figs. 6A & 6B)
Probes are placed on the pins, and measurements are acquired at 0.4V.
The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is stable and operating
within the specifications
Applicable only to clocks within the same bank
The cycle to cycle jitter of the device is dependent on 2 factors. They are the jitter component of the input reference clock and whether the 2
output clock banks are operating at the same frequency, When the frequency of the output banks is the same, output jitter is guaranteed to
not be more than 175pSec. When the output clocks of each bank differ in frequency, the device is guaranteed to be no more than 250
pSec.
ns
1, 2, 4
THIGH
TLOW
3
3
-
-
4
4
-
-
6
6
-
-
11
11
-
-
ns
ns
2,6
2, 7
Tr / Tf
0.50
1.33
0.50
1.33
0.50
1.33
0.50
1.33
ns
2, 3
TSKEW
-
250
-
250
-
250
-
250
ps
2, 4,
5. 9
2, 4,
5, 10
2, 3
2, 4
TCCJ
250 or 175
(see note 10)
4.0
750
ps
Tr / Tf
TCCJ
1.0
4.0
1.0
1.0
4.0
1.0
4.0
ns
ps
tpZL, tpZH
-
10.0
-
10.0
-
10.0
-
10.0
ns
tpLZ, tpHZ
-
10.0
-
10.0
-
10.0
-
10.0
ns
tstable
-
3
-
3
-
3
-
3
ms
8
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note10:
Output Name
REF
CLK(A:B)(0:4)
Max Load (in pF)
20
30
Table 1
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