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參數(shù)資料
| 型號(hào)： | C9815DY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 328K |
| 代理商： | C9815DY |
Low EMI Clock Generator for Intel
133MHz/2DIMM Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07054 Rev. **
05/03/2001
Page 13 of 19
APPROVED PRODUCT
C9815
133 MHz Host
Min
69.8413
1.0
-
1.0
1.0
100 MHz Host
Min
69.8413
1.0
-
1.0
1.0
66 MHz Host
Min
Symbol
Parameter
Max
71.0
4.0
1000
10.0
10.0
3
55
Max
71.0
4.0
1000
10.0
10.0
3
55
Max
Units
TPeriod
Tr / Tf
TCCJ
tpZL, tpZH
tpLZ, tpHZ
tstable
Tduty
REF period
5,6
REF rise and fall times
7
REF Cycle to Cycle Jitter
6
Output enable delay (all outputs)
8
Output disable delay (all outputs)
13
All clock Stabilization from power-up
12
Duty Cycle for All outputs
14
69.8413
1.0
-
1.0
1.0
71.0
4.0
1000
10.0
10.0
3
55
nS
nS
pS
nS
nS
mS
%
45
45
45
Note 5:
This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6:
All outputs loaded as per table 5, page 11. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at
1.25V for 2.5V signals (figs. 9A and 9B).
Note 7:
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Fig.9A and Fig.9B)
Note 8:
Measured from when both SEL1 and SEL0 are switched to high (enable).
Note 9:
This measurement is applicable with Spread ON or Spread OFF.
Note 10:
Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figs. 9A & 9B)
Note 11:
Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:
The time specified is measured from when all VDD
’
s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 13:
Measured from when both SEL1 and SEL0 are switched to low (disable).
Note 14:
Device designed for Typical Duty Cycle of 50%.
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