參數(shù)資料
型號(hào): C9815DY
英文描述: Up to 5A ULDO linear regulator
中文描述: CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料
文件頁(yè)數(shù): 9/19頁(yè)
文件大?。?/td> 328K
代理商: C9815DY
Low EMI Clock Generator for Intel
133MHz/2DIMM Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07054 Rev. **
05/03/2001
Page 9 of 19
APPROVED PRODUCT
C9815
SMBUS Test Circuitry
Fig.7
Note: Buffer is 7407 with VCC @ 5.0 V
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
distributing an even amount of energy over a wider spectrum. This technique is achieved by modulating the clock either
down (Fig.8A) or around the center (Fig.8B) of its resting frequency by a certain percentage (which also determines the
energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS byte0, bit3 = 1. The
default of the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have SMBUS
accessibility to turn-on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth
option is selected by SST(0:2) in SMBUS byte 5, bits 5, 6 & 7 following tables 4A, and 4B below.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by
of the total spread
%. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of
0.5% is enabled, the
center frequency shifts to 99.75MHz.).
2.2 K
Device under Test
SDATA
DATAIN
SCLK
DATAOUT
CLOCK
+ 5V
+ 5V
+ 5V
2.2 K
2.2 K
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