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參數(shù)資料
| 型號： | C9815DY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 328K |
| 代理商： | C9815DY |
Low EMI Clock Generator for Intel
133MHz/2DIMM Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07054 Rev. **
05/03/2001
Page 7 of 19
APPROVED PRODUCT
C9815
2-Wire SMBUS Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See Fig. 6
below). The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported, thus
all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each
clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. The LSB address Byte = 0 in write mode.
The device will respond to transfers of 10 bytes (max) of data. The device will generate an acknowledge (low) signal on
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. This device
will also respond to a D3 address which sets it in a read mode. It will not respond to any other control interface
conditions, and previously set control registers are retained.
START CONDITION
Transmit
Receive
STOP CONDITION
START CONDITION
Transmit
Receiv
STOP CONDITION
1
8
ACK
MSB
0
0
0
DATA
0
1
LSB
COMMAND BYTE
1
CLK
1
BYTE N
8
8
8
BYTE 0
BYTE COUNT
ACK
ACK
ACK
ACK
(Don
’
t Care)
(Don
’
t Care)
(Valid)
(Valid)
Fig.6a
(WRITE)
(Valid)
DATA
1
0
(Valid)
0
1
1
8
BYTE N
(Valid)
BYTE COUNT
CLK
LSB
ACK
8
ACK
ACK
8
0
BYTE1
1
ACK
ACK
MSB
8
1
(Valid)
BYTE 0
Fig.6b (READ)
Figure 6
SMBUS Communications Waveforms
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