參數(shù)資料
型號: CA3130SX
英文描述: TRANSIL
中文描述: 電壓反饋運算放大器
文件頁數(shù): 11/15頁
文件大?。?/td> 617K
代理商: CA3130SX
2-118
CA3130, CA3130A
FIGURE 17. 18-9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
20Vp-p Input: BW(-3dB) = 230kHz, DC Output (Avg.) = 3.2V
1Vp-p Input: BW(-3dB) = 130kHz, DC Output (Avg.) = 160mV
Top Trace:
Bottom Trace:
Time base on both traces:
Output Signal (2V/div.)
Input Signal (10V/div.)
0.2ms/div.
FIGURE 18. SINGLE-SUPPLY, ABSOLUTE-VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
6
3
10
10
3
6
4
8
3
6
7
9
4
10
2
3
13
8
1
5
12
12
1
5
8
13
13
1
12
8
5
14
11
2
6
5
1
7
7
1
6
8
4
3
2
10V LOGIC INPUTS
+10.010
LSB
9
8
7
6
5
4
3
2
1
MSB
806K
1%
PARALLELED
RESISTORS
10K
+15V
VOLTAGE
FOLLOWER
CA3130
OUTPUT
LOAD
100K
OFFSET
NULL
56pF
2K
0.1
μ
F
REGULATED
VOLTAGE
ADJ
3 83K
1%
22 1K
1%
1K
0.001
μ
F
CA3085
VOLTAGE
REGULATOR
+15V
2
μ
F
25V
+
-
+10.010
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
402K
1%
200K
1%
100K
1%
806K
1%
806K
1%
806K
1%
750K
1%
806K
1%
806K
1%
806K
1%
806K
1%
(2)
(4)
(8)
806K
1%
+
-
62
BIT
1
2
3
4
5
6 - 9
ALL RESISTANCES IN OHMS
REQUIRED
RATIO-MATCH
STANDARD
±
0.1%
±
0.2%
±
0.4%
±
0.8%
±
1% ABS
2
3
4
6
8
1
5
7
R2
2k
+15V
0.01
μ
F
IN914
R3
5.1k
PEAK
ADJUST
2k
100k
OFFSET
ADJUST
20pF
CA3130
+
R1
4k
-
Gain
R2
R1
X
R3
R2
R1
R3
+
+
=
=
=
R3
R1
X
X2
X
+
2k
4k
1
(
)
=
For X
0.5:
R2
R1
=
=
R3
4k
0.75
0.5
(
)
6k
=
=
-0V
-0V
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