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參數(shù)資料
| 型號： | CA3130SX |
| 英文描述： | TRANSIL |
| 中文描述： | 電壓反饋運(yùn)算放大器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 617K |
| 代理商： | CA3130SX |
2-112
CA3130, CA3130A
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply con-
necting a small capacitor between Terms. 1 and 8. A 47-
picofarad capacitor provides sufficient compensation for sta-
ble unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3 volts, resistor
R2 and zener diode Z1 serve to establish a voltage of 8.3 volts
across the series-connected circuit, consisting of resistor R1,
diodes D1 through D4, and PMOS transistor Q1. A tap at the
junction of resistor R1 and diode D4 provides a gate-bias
potential of about 4.5 volts for PMOS transistors Q4 and Q5
with respect to Term. 7. A potential of about 2.2 volts is devel-
oped across diode-connected PMOS transistor Q1 with
respect to Term. 7 to provide gate bias for PMOS transistors
Q2 and Q3. It should be noted that Q1 is “mirror-connected”*
to both Q2 and Q3. Since transistors Q1, Q2, Q3 are
designed to be identical, the approximately 200-microampere
current in Q1 establishes a similar current in Q2 and Q3 as
constant current sources for both the first and second ampli-
fier stages, respectively.
At total supply voltages somewhat less than 8.3 volts, zener
diode Z1 becomes nonconductive and the potential, devel-
oped across series-connected R1, D1-D4, and Q1, varies
directly with variations in supply voltage. Consequently, the
gate bias for Q4, Q5 and Q2, Q3 varies in accordance with
supply-voltage variations. This variation results in deteriora-
tion of the power-supply-rejection ratio (PSRR) at total sup-
ply voltages below 8.3 volts. Operation at total supply
voltages below about 4.5 volts results in seriously degraded
performance.
Output Stage
The output stage consists of a drain-loaded inverting ampli-
fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer charac-
teristics of the output stage for a load returned to the nega-
tive supply rail are shown in Figure 5. Typical op-amp loads
are readily driven by the output stage. Because large-signal
excursions are non-linear, requiring feedback for good wave-
form reproduction, transient delays may be encountered. As
a voltage follower, the amplifier can achieve 0.01 percent
accuracy levels, including the negative supply rail.
* For general information on the characteristics of CMOS transistor-
pairs in linear-circuit applications, see File Number 619, data bulle-
tin on CA3600E “CMOS Transistor Array”.
FIGURE 2. BLOCK DIAGRAM OF THE CA3130 SERIES
FIGURE 3. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT
vs FREQUENCY
3
2
-
7
4
8
1
5
6
BIAS CKT.
COMPENSATION
(WHEN REQUIRED)
A
V
≈
5X
A
≈
6000X
A
≈
30X
INPUT
+
200
μ
A
200
μ
A
1.35mA
8mA*
0mA**
V+
OUTPUT
V-
STROBE
C
C
OFFSET
NULL
CA3130
TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) = 15V
*WITH INPUT TERMINALS BIASED SO THAT TERM. 6 POTENTIAL
IS +7.5V ABOVE TERM. 4.
**WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL.
SUPPLY VOLTAGE: V+ = 15V; V- = 0
T
A
= +25
o
C
φ
OL
3
2
1
1
2
3
4
4
CAPACITANCE: LOAD (C
L
) = 9pF
COMPENSATION (C
C
) = 0
10
2
10
3
10
1
AOL
1 = LOAD RESISTANCE (R
L
) =
∞
2 = C
L
= 30pF, C
C
= 15pF, R
L
= 2k
3 = C
L
= 30pF, C
C
= 47pF, R
L
= 2k
4 = C
L
= 30pF, C
C
= 150pF, R
L
= 2k
120
100
80
60
40
20
0
O
-100
-200
-300
O
10
4
10
5
10
6
10
7
10
8
FREQUENCY (Hz)
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