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參數(shù)資料
| 型號： | CDC2509BPWG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DVR 3.3V 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | PLL 時鐘驅(qū)動器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
CDC2509B
3.3V PHASELOCK LOOP CLOCK DRIVER
SCAS613C SEPTEMBER 1998 REVISED DECEMBER 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC, AVCC
MIN
TYP
MAX
UNIT
VIK
II = 18 mA
3 V
1.2
V
IOH = 100 A
MIN to MAX
VCC0.2
VOH
IOH = 12 mA
3 V
2.1
V
VOH
IOH = 6 mA
3 V
2.4
V
IOL = 100 A
MIN to MAX
0.2
VOL
IOL = 12 mA
3 V
0.8
V
VOL
IOL = 6 mA
3 V
0.55
V
II
VI = VCC or GND
3.6 V
±5
A
ICC
VI = VCC or GND,
IO = 0, Outputs: low or high
3.6 V
10
A
ICC
One input at VCC 0.6 V,
Other inputs at VCC or GND
3.3 V to 3.6 V
500
A
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
6
pF
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For ICC of AVCC, and ICC vs Frequency (see Figures 7 and 8).
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclk
Clock frequency
25
125
MHz
Input clock duty cycle
40%
60%
Stabilization time§
1
ms
§ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
± 0.165 V
VCC, AVCC = 3.3 V
± 0.3 V
UNIT
PARAMETER
(INPUT)/CONDITION
(OUTPUT)
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tphase error, jitter
(see Notes 7 and 8,
Figures 3, 4, and 5)
CLKIN
↑ = 66 MHz to100 MHz
FBIN
↑
150
200
ps
tsk(o)#
Any Y or FBOUT
200
ps
Jitter(pk-pk)
(see Figure 6)
CLKIN = 66 MHz to 100 MHz
Any Y or FBOUT
80
ps
Jitter(cycle-cycle)
(see Figure 6)
CLKIN = 66 MHz to 100 MHz
Any Y or FBOUT
|100|
ps
Duty cycle
F(CLKIN > 60 MHz)
Any Y or FBOUT
45%
55%
tr
Any Y or FBOUT
1.3
1.9
0.8
2.1
ns
tf
Any Y or FBOUT
1.7
2.5
1.2
2.7
ns
These parameters are not production tested.
# The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is 230 ps to 230 ps for the 5% VCC range.
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| CDC2509BPWLE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Nine Distributed-Output Clock Driver |
| CDC2509BPWR | 功能描述:時鐘驅(qū)動器及分配 3.3V Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2509BPWRG4 | 功能描述:時鐘驅(qū)動器及分配 3.3V Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2509BSTE-E | 功能描述:IC 3.3V PLL CLOCK DVR 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| CDC2509C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
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