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參數(shù)資料
| 型號： | CDC2509BPWG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DVR 3.3V 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | PLL 時鐘驅(qū)動器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
CDC2509B
3.3V PHASELOCK LOOP CLOCK DRIVER
SCAS613C SEPTEMBER 1998 REVISED DECEMBER 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PACKAGE
TA
SMALL OUTLINE
(PW)
0
°C to 70°C
CDC2509BPWR
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDC2509B and the CDC2510B clock
drivers. CLK is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the
circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to
phase lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
1G
11
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
2G
14
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-
series-damping resistor.
1Y (0:4)
3, 4, 5, 8, 9
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-
series-damping resistor.
2Y (0:3)
16, 17, 20, 21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-
series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 15, 22
Power
Power supply
GND
6, 7, 18, 19
Ground
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC2509BPWLE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Nine Distributed-Output Clock Driver |
| CDC2509BPWR | 功能描述:時鐘驅(qū)動器及分配 3.3V Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2509BPWRG4 | 功能描述:時鐘驅(qū)動器及分配 3.3V Clock RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2509BSTE-E | 功能描述:IC 3.3V PLL CLOCK DVR 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| CDC2509C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
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