參數(shù)資料
型號(hào)： CH5101A
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： CMOS Monochrome Digital Video Camera
中文描述： 單色的CMOS數(shù)碼攝像機(jī)
文件頁(yè)數(shù)： 28/32頁(yè)
文件大?。?/td> 132K
代理商： CH5101A
28
201-0000-033 Rev 1.0, 6/2/99
CHRONTEL
CH5101A
Miscellaneous Register 3
Symbol:MISC3
Address:23h
Bits:6
Bits 0-3 (Clock Delay) of register MISC3 determine the clock delay between the analog and digital clocks. The
recommended value is 9
Bit 7 (A/D Full Scale Range) of register MISC3 changes the full scale range of the AD converter. A 0 in this
location sets the A/D full scale range at + 1 volt. A 1 in this location sets the A/D full scale range at +0.25 volt. This
bit can be combined with the PSHG[2:0] to form a 4-bit control.
Power Down Register
Symbol:PD
Address:24h
Bits:3
Bits 2-0 of register PD are used to power down portions of circuitry during test modes. These bits should always be
set to zero during normal operation.
Bit 4 of register PD is used to perform a software reset on the device. It is logically AND’d with the power on reset
signal. The output of this AND’ing will be used to reset all circuitry in the CH5101, except for the ResetB bit itself
and the IIC state machines. ResetB and the IIC state machines are reset by the power on reset signal only.
Address Register
Symbol:AR
Address:26h
Bits:8
Register AR is the CH5101 address register, which holds the address of the register currently being accessed.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
ADFSR
Reserved
Reserved
Reserved
CKDLY3
CKDLY2
CKDLY1
CKDLY0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT:
0
0
1
1
1
0
0
1
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
ResetB
Reserved
PD2
PD1
PD0
TYPE:
DEFAULT:
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
TYPE:
DEFAULT:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
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