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CHRONTEL
CH5101A
201-0000-033 Rev 1.0, 6/2/99
29
Electrical Specifications
Notes:
1
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce
destructive latch.
Table 13. Absolute Maximum Ratings
Symbol
Description
Min
- 0.5
Typ
Max
7.0
Units
V
V
°
C
°
C
°
C
V
DD
relative to GND
Input voltage of all digital pins
1
Storage temperature
Junction temperature
Vapor phase soldering (one minute)
GND - 0.5
- 65
Vdd + 0.5
150
150
220
T
STOR
T
J
T
VPS
Table 14. Recommended Operating Conditions
Symbol
DV
DD
AV
DD
T
A
Description
Min
Typ
Max
Unit
Digital supply voltage
Analog supply voltage
Ambient operating temperature
4.75
4.75
0
5.00
5.00
25
5.25
5.25
40
V
V
C
Table 15. Digital Inputs/Outputs
Symbol
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Test Condition @TA= 25
°
C
Ioh =.400 mA
Iol = 3.2 mA
Min
Typ
Max
Unit
Voh
2.8
V
V
V
V
μ
A
Vol
0.4
V
DD
0.8
10
Vih
3.4
GND
-10
Vil
Ilk
Table 16. Timing Characteristics
Symbol
t
VSW
t
HSW
t
HD
t
P
t
PH
t
PH
t
SP
t
HP
Description
Min
Typ
Max
Unit
Vertical sync pulse width
Horizontal sync pulse width
Horizontal and vertical sync delay from clock
CLKOUT period (varies with mode and output format)
CLKOUT high time
CLKOUT low time
CLKOUT to pixel data setup time
CLKOUT to pixel data hold time
2
64
Lines
MCLK
nS
nS
nS
nS
ns
ns
2
37
14.8
14.8
2
2
10
148.2
89
89