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參數資料
| 型號： | COP8CDR9HVA8/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數： | 44/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 44-PLCC |
| 標準包裝： | 25 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數： | 37 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數據轉換器： | A/D 16x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9HVA8 *COP8CDR9HVA8/NOPB COP8CDR9HVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
The method to force this condition is to drive the G6 pin to high voltage (2 x VCC) and activate Reset. The
high voltage condition on G6 must not be applied before VCC is valid and stable, and must be held for at
least 3 instruction cycles longer than Reset is active. This special condition will bypass checking the state
of the Flex bit in the Option Register and will start execution from location 0000 in the Boot ROM. In this
state, the user can input the appropriate commands, using MICROWIRE/PLUS, to erase the flash
program memory and reprogram it. If the device is subsequently reset before the Flex bit has been erased
by specific Page Erase or Mass Erase ISP commands, execution will start from location 0000 in the Flash
program memory. The high voltage (2 x VCC) on G6 will not erase either the Flex or the Security bit in the
Option Register. The Security bit, if set, can only be erased by a Mass Erase of the entire contents of the
Flash Memory unless under the control of User ISP routines in the Application Program.
While the G6 pin is at high voltage, the Load Clock will be output onto G5, which will look like an SK clock
to the MICROWIRE/PLUS routine executing in slave mode. However, when G6 is at high voltage, the G6
input will also look like a logic 1. The MICROWIRE/PLUS routine in Boot ROM monitors the G6 input,
waits for it to go low, debounces it, and then enables the ISP routine. CAUTION: The Load clock on G5
could be in conflict with the user's external SK. It is up to the user to resolve this conflict, as this condition
is considered a minor issue that's only encountered during software development. The user should also
be cautious of the high voltage applied to the G6 pin. This high voltage could damage other
circuitry connected to the G6 pin (e.g. the parallel port of a PC). The user may wish to disconnect
other circuitry while G6 is connected to the high voltage.
VCC must be valid and stable before high voltage is applied to G6.
The correct sequence to be used to force execution from Boot ROM is :
1. Disconnect G6 from the source of data for MICROWIRE/PLUS ISP.
2. Apply VCC to the device.
3. Pull RESET Low.
4. After VCC is valid and stable, connect a voltage between 2 x VCC and VCC+7V to the G6 pin. Ensure
that the rise time of the high voltage on G6 is slower than the minimum in the Electrical Specifications.
Figure 5-8 shows a possible circuit dliagram for implementing the 2 x VCC. Be aware of the typical input
current on the G6 pin when the high voltage is applied. The resistor used in the RC network, and the
high voltage used, should be chosen to keep the high voltage at the G6 pin between 2 x VCC and
VCC+7V.
5. Pull RESET High.
6. After a delay of at least three instruction cycles, remove the high voltage from G6.
Figure 5-8. Circuit Diagram for Implementing the 2 x VCC
5.10.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET
After programming the entire program memory, including options, it is necessary to exit the Boot ROM and
return to the flash program memory for program execution. Upon receipt and completion of the EXIT
command through the MICROWIRE/PLUS ISP, the ISP code will reset the part and begin execution from
the flash program memory as described in the Reset section. This assumes that the FLEX bit in the
Option register was programmed to 1.
38
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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