參數(shù)資料
型號： COP8CDR9HVA8/NOPB
廠商： National Semiconductor
文件頁數(shù)： 96/111頁
文件大?。?/td> 0K
描述： IC MCU CMOS 8BIT 44-PLCC
標(biāo)準(zhǔn)包裝： 25
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
其它名稱： *COP8CDR9HVA8
*COP8CDR9HVA8/NOPB
COP8CDR9HVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.17.1 MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets
reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less
than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device
may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 5-26 shows how two
microcontroller devices and several peripherals may be interconnected using the MICROWIRE/PLUS
arrangements.
WARNING
The SIO register should only be loaded when the SK clock is in the idle phase.
Loading the SIO register while the SK clock is in the active phase, will result in
undefined data in the SIO register.
Setting the BUSY flag when the input SK clock is in the active phase while in the
MICROWIRE/PLUS is in the slave mode may cause the current SK clock for the
SIO shift register to be narrow. For safety, the BUSY flag should only be set when
the input SK clock is in the idle phase.
5.17.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The
MICROWIRE/PLUS Master always initiates all data exchanges. The MSEL bit in the CNTRL register must
be set to enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as
outputs by setting appropriate bits in the Port G configuration register. In the slave mode, the shift clock
stops after 8 clock pulses. Table 5-30 summarizes the bit settings required for Master mode of operation.
5.17.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source.
Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin
must be selected as an input and the SO pin is selected as an output pin by setting and resetting the
appropriate bits in the Port G configuration register. Table 5-30 summarizes the settings required to enter
the Slave mode of operation.
Table 5-30. MICROWIRE/PLUS Mode Settings
G4 (SO)
G5 (SK)
G4
G5
Operation
Config. Bit
Fun.
1
SO
Int.
MICROWIRE/PLUS
SK
Master
0
1
TRI-
Int.
MICROWIRE/PLUS
STATE
SK
Master
1
0
SO
Ext.
MICROWIRE/PLUS
SK
Slave
0
TRI-
Ext.
MICROWIRE/PLUS
STATE
SK
Slave
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
85
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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