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參數(shù)資料
| 型號： | COP8CDR9HVA8/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 53/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 44-PLCC |
| 標準包裝： | 25 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9HVA8 *COP8CDR9HVA8/NOPB COP8CDR9HVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-11. Timer in External Event Counter Mode
5.11.2.4 Mode 3. Input Capture Mode
The device can precisely measure external frequencies or time external events by placing the timer block,
Tx, in the input capture mode. In this mode, the reload registers serve as independent capture registers,
capturing the contents of the timer when an external event occurs (transition on the timer input pin). The
capture registers can be read while maintaining count, a feature that lets the user measure elapsed time
and time between events. By saving the timer value when the external event occurs, the time of the
external event is recorded. Most microcontrollers have a latency time because they cannot determine the
timer value when the external event occurs. The capture register eliminates the latency time, thereby
allowing the applications program to retrieve the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed tC or MCLK rate. The two registers, RxA and
RxB, act as capture registers. Each register also acts in conjunction with a pin. The register RxA acts in
conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a trigger event occurs on its corresponding pin
after synchronization to the appropriate internal clock (tC or MCLK). Control bits, TxC3, TxC2 and TxC1,
allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for
each input pin can be specified independently.
The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified
trigger condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and
TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the
TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin.
Similarly, the flag TxENB controls the interrupts from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the
timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the
Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture
mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs
in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to
determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.
Figure 5-12 shows a block diagram of the timer T1 in Input Capture mode. T2 and T3 are identical to T1.
46
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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