參數(shù)資料
型號(hào)： CR16HCT9VJE7
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 138/157頁
文件大?。?/td> 1256K
代理商： CR16HCT9VJE7
www.national.com
138
Analog Comparator Characteristics
Flash EEPROM Program Memory Programming
Symbol
V
OS
Parameter
Conditions
Min
Typ
Max
Units
Input Offset Voltage
Vcc = 5V,
0.4V
≤
V
IN
≤
V
CC
–
1.5V
±
25
mV
V
CM
I
CS
Input Common Mode Voltage Range
DC Supply Current per Comparator (When
Enabled)
Response Time
0.4
V
CC
-1.5
V
V
CC
=5.5V
250
μ
A
1V Step / 100mV Overdrive
1
μ
s
Symbol
Parameter
Conditions
Min
Max
Units
t
PWP
t
EWP
t
SDP
t
TTP
t
PAH
Programming pulse width
a
Erase pulse width
b
Charge pump power-up delay
c
Program/erase transition time
d
Programming address hold, new address setup
time
Charge pump enable hold time
a. The programming pulse width is determined by the following equation:
t
PWP
= T
clk
x (FTDIV+1) x (FTPROG+1), where T
clk
is the system clock period, FTDIV is the contents of the FLPSLR register
and FTPROG is the contents of the FLPROG register.
30
4
10
5
2
40
-
-
-
-
μ
s
ms
μ
s
μ
s
clock
cycles
clock
cycles
μ
s
ms
b. The erase pulse width is determined by the following equation:
t
EWP
= T
clk
x (FTDIV+1) x 4 x (FTER+1), where T
clk
is the system clock period, FTDIV is the contents of the FLPSLR register
and FTER is the contents of the FLERASE register.
c. The program/erase start delay time is determined by the following equation:
t
SDP
= T
clk
x (FTDIV+1) x (FTSTART+1), where T
clk
is the system clock period, FTDIV is the contents of the FLPSLR register
and FTSTART is the contents of the FLSTART register.
d. The program/erase transition time is determined by the following equation:
t
TTP
= T
clk
x (FTDIV+1) x (FTTRAN+1), where T
clk
is the system clock period, FTDIV is the contents of the FLPSLR register and
FTTRAN is the contents of the FLTRAN register.
t
PEP
1
-
t
EDP
t
CHVP
Charge pump power hold time
e
Cumulative program high voltage period for each
row after erase.
f
Data retention
e. The program/erase end delay time is determined by the following equation:
t
EDP
= T
clk
x (FTDIV+1) x (FTEND+1), where T
clk
is the system clock period, FTDIV is the contents of the FLPSLR register and
FTEND is the contents of the FLEND register.
5
-
f. Cumulative program high voltage period for each row after erase t
CHVP
is the accumulated duration a flash cell is exposed to the
programming voltage after the last erase cycle. It is the sum of all t
HV
after the last erase.
25
100
-
-
years
cycles
100K
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