參數(shù)資料
型號(hào)： CR16HCT9VJE7
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 148/157頁
文件大?。?/td> 1256K
代理商： CR16HCT9VJE7
www.national.com
148
25.0.2
Timing Tables
Table 45
Output Signals
Symbol Figure
Tclk
a
Description
Reference
Min (ns) Max (ns)
77
CLK clock period
CLK high time
R.E. CLK to next R.E. CLK
At 2.0V
(Both Edges)
At 0.8V
(Both Edges)
0.8V to 2.0V
2.0V to 0.8V
After R.E. CLK
41.66
64000
a
t
CLKh
77
17.3
t
CLKl
77
CLK low time
17.3
t
CLKr
t
CLKf
77
77
CLK rise time on R.E. CLK
CLK fall time on F.E. CLK
CMOS output valid
All signals with prop. delay from CLK
R.E.
3
3
t
COv1
35
USART Output Signals
t
TXD
84
TXDn output valid
After R.E. CLKXn
35
MICROWIRE / SPI Output Signals
t
MSKh
t
MSKl
86
86
MICROWIRE Clock High
MICROWIRE Clock Low
MICROWIRE Clock Period
At 2.0V (both edges)
At 0.8V (both edges)
MnIDL bit = 0: R.E. MSK to next R.E.
MSKn
MnIDL bit = 1: F.E. MSK to next F.E.
MSKn
Data Out Bit #7 Valid
80
80
t
MSKp
86
200
87
t
MSKd
86
MSK Leading Edge Delayed (master
only)
MICROWIRE Data Float
b
(slave only)
MICROWIRE Data Out Hold
0.5 t
MSK
1.5 t
MSK
t
MDOf
86
After R.E. MCSn
56
t
MDOh
86
Normal Mode: After F.E. MSK
Alternate Mode: After R.E. MSK
0.0
t
MDOnf
90
MICROWIRE Data No Float
(slave only) After F.E. MWCS
MICROWIRE Data Out Valid
0
56
t
MDOv
86
Normal Mode: After F.E. MSK
Alternate Mode: After R.E. MSK
Propagation Time
Value is the same in all clocking modes of
the MICROWIRE
56
t
MITOp
MDODI to MDIDO
(slave only)
56
90
CAN Output Signals
t
CANTx
CANTx output valid
After R.E. CLKXn
13
ACCESS.bus Output Signals
t
BUFo
89
Bus free time between Stop and Start
Condition
SCL setup time
SCL hold time
SCL setup time
Data High setup time
t
SCLhigho
t
CSTOso
t
CSTRho
t
CSTRso
t
DHCso
89
89
90
90
Before Stop Condition
After Start Condition
Before Start Condition
Before SCL R.E.
t
SCLhigho
t
SCLhigho
t
SCLhigho
t
SCLhigho
-t
SDAro
t
SCLhigho
-t
SDAfo
t
DLCso
89
Data Low setup time
Before SCL R.E.
t
SCLfo
t
SCLro
88
88
SCL signal Fall time
SCL signal Rise time
300
c
-
d
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