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參數(shù)資料
| 型號： | CS2100P-DZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 中文描述： | PHASE LOCKED LOOP, 30 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 223K |
| 代理商： | CS2100P-DZZR |
CS2100-OTP
DS841F2
7
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
TA = -40°C to +85°C (Automotive Grade); CL =15pF.
Notes: 5.
1 UI (unit interval) corresponds to tSYS_CLK or 1/fSYS_CLK.
6.
7.
In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8.
In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9.
1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
Parameters
Symbol
Conditions
Min
Typ
Max
Units
Crystal Frequency
Fundamental Mode XTAL
fXTAL
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
-
18.75
37.5
50
MHz
Reference Clock Input Frequency
fREF_CLK
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
-
18.75
37.5
75
MHz
Reference Clock Input Duty Cycle
DREF_CLK
45
-
55
%
Internal System Clock Frequency
fSYS_CLK
8
18.75
MHz
Clock Input Frequency
fCLK_IN
50 Hz
-
30
MHz
Clock Input Pulse Width (Note 5)pwCLK_IN
fCLK_IN < fSYS_CLK/96
fCLK_IN > fSYS_CLK/96
2
10
-
UI
ns
PLL Clock Output Frequency
fCLK_OUT
6-
75
MHz
PLL Clock Output Duty Cycle
tOD
Measured at VD/2
45
50
55
%
Clock Output Rise Time
tOR
20% to 80% of VD
-
1.7
3.0
ns
Clock Output Fall Time
tOF
80% to 20% of VD
-
1.7
3.0
ns
Period Jitter
tJIT
-
70
-
ps rms
Base Band Jitter (100 Hz to 40 kHz)
(Notes 6, 7)
-
50
-
ps rms
Wide Band JItter (100 Hz Corner)
(Notes 6, 8)
-
175
-
ps rms
PLL Lock Time - CLK_IN (Note 9)tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
100
1
200
3
UI
ms
PLL Lock Time - REF_CLK
tLR
fREF_CLK = 8 to 75 MHz
-
1
3
ms
Output Frequency Synthesis Resolution (Note 10)ferr
High Resolution
0
-
±0.5
±112
ppm
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