5.26 Misc. Crystal Control Register (Index 60h) DPC DAC Phase Control. This bit controls the phase of the PCM stream " />
參數(shù)資料
型號: CS4205-KQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 39/81頁
文件大?。?/td> 0K
描述: IC CODEC AC97 I2S 48-LQFP
標準包裝: 250
類型: 音頻編解碼器 '97
數(shù)據(jù)接口: 串行
分辨率(位): 18,20 b
ADC / DAC 數(shù)量: 1 / 2
三角積分調(diào)變:
動態(tài)范圍,標準 ADC / DAC (db): 90 / 90
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(9x9)
包裝: 托盤
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
其它名稱: 598-1182
CS4205
44
DS489PP4
5.26
Misc. Crystal Control Register (Index 60h)
DPC
DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs (after
SRC). When ‘cleared’ the phase of the signal will remain unchanged. When this bit is ‘set’,
each PCM sample will be inverted before being sent to the DACs.
10dB
Microphone 10 dB Boost. When ‘set’, the 10dB bit enables an additional boost of 10 dB on
the selected microphone input. In combination with the 20dB boost bit in the Microphone Vol-
ume Register (Index 0Eh) this bit allows for variable boost from 0 dB to +30 dB in steps of
10 dB.
CRST
Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior
defined during PR4 powerdown. If this bit is ‘set’, an active RESET# signal will force a Cold
Reset to the CS4205 during a PR4 powerdown.
GPOC
General Purpose Output Control. The GPOC bit specifies the mechanism by which the status
of a General Purpose Output pin can be controlled. If this bit is ‘cleared’, the GPO status is
controlled through the standard AC ’97 method of setting the appropriate bits in output
Slot 12. If this bit is ‘set’, the GPO status is controlled through the GPIO Pin Status Register
(Index 54h).
LOSM
Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit
is ‘set’, the CS4205 will mute all analog outputs for the duration of loss of SYNC. If this bit is
‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4205 ex-
pects to sample SYNC ‘high’ for 16 consecutive BIT_CLK periods and then ‘low’ for 240 con-
secutive BIT_CLK periods, otherwise loss of SYNC becomes true.
Default
0003h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Res
DPC
0
Reserved
10dB
CRST
Reserved
GPOC
Reserved
LOSM
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