5.28 Serial Port Control Register (Index 6Ah) SDEN Serial Data Output Enable. The SDEN bit enables transmission of se" />
參數(shù)資料
型號(hào)： CS4205-KQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 41/81頁
文件大?。?/td> 0K
描述： IC CODEC AC97 I2S 48-LQFP
標(biāo)準(zhǔn)包裝： 250
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18，20 b
ADC / DAC 數(shù)量： 1 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 90 / 90
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 754 (CN2011-ZH PDF)
其它名稱： 598-1182
CS4205
46
DS489PP4
5.28
Serial Port Control Register (Index 6Ah)
SDEN
Serial Data Output Enable. The SDEN bit enables transmission of serial data on the SDOUT
pin. The SDEN bit routes the left and right channel data from the AC ’97 controller, the digital
mixer, or the digital effects engine to the serial data port. The actual data routed to the serial
data port are controlled through the SDOS[1:0]/AMAP/SM[1:0] configuration in the AC Mode
Control Register (Index 5Eh). SDEN also functions as a master control for the serial data input
ports, the second serial data output port and the serial clock. Setting this bit also disables the
GPIO[1:0] pins and clears the GC[1:0] bits in the GPIO Pin Configuration Register (Index
4Ch). Clearing this bit re-enables the GPIO[1:0] pins and sets the GC[1:0] bits.
SDI[3:1]
Serial Data Input Enable. The SDI[3:1] bits individually enable the reception of serial data on
the SDI[3:1] pins. Each of these bits routes the left and right channel data from the corre-
sponding serial data input port to its associated volume control. These bits can only be set if
the SDEN bit is ‘1’ and will be cleared automatically if SDEN returns to ‘0’. If the SDEN bit is
‘0’, SDI[3:1] are read-only bits and always return ‘0’. If allowed, setting one of these bits also
disables the corresponding GPIO pin and clears the associated GC bit for this pin in the GPIO
Pin Configuration Register (Index 4Ch). Clearing one of these bits re-enables the correspond-
ing GPIO pin and sets the associated GC bit.
SDO2
Serial Data Output 2 Enable. The SDO2 bit enables transmission of serial data on the SP-
DO/SDO2 pin. The SDO2 bit routes the left and right channel data from the AC ’97 controller
to the second serial data port. The actual slots routed to the second serial data port are con-
trolled through the AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh).
This bit can only be ‘set’ if the SDEN bit is ‘1’ and will be ‘cleared’ automatically if SDEN re-
turns to ‘0’. Furthermore, the SDO2 bit can only be ‘set’ if the SPEN bit in the S/PDIF Control
Register (Index 68h) is ‘0’. If the SDEN bit is ‘0’ or the SPEN bit is ‘1’, SDO2 is a read-only bit
and always returns ‘0’.
SDSC
Serial Clock Enable. The SDSC bit enables transmission of a serial clock on the EAPD/SCLK
pin. Serial data can be routed to DACs that support internal SCLK mode without transmitting
a serial clock. For DACs that only support external SCLK mode, transmission of a serial clock
is required and this bit must be set to ‘1’. This bit can only be set if the SDEN bit is ‘1’ and will
be cleared automatically if SDEN returns to ‘0’. Furthermore, the SDSC bit can only be ‘set’
if the EAPD bit in the Powerdown Control/Status Register (Index 26h) is ‘0’. If the SDEN bit
is ‘0’ or the EAPD bit is ‘1’, SDSC is a read-only bit and always returns ‘0’.
SDF[1:0]
Serial Data Format. The SDF[1:0] bits control the format of the serial data transmitted on the
two output ports and the three input ports. All ports will use the same format. See Table 16
for available formats.
Default
0000h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDEN
0
SDI3
SDI2
SDI1
SDO2 SDSC SDF1
SDF0
SDF1 SDF0
Serial Data Format
00
I2S
0
1
Left Justified
1
0
Right Justified, 20-bit data
1
Right Justified, 16-bit data
Table 16. Serial Data Format Selection
相關(guān)PDF資料
PDF描述
CS4207-DNZ IC CODEC AUD HDPN AMP AUTO 48QFN
CS4265-CNZ IC CODEC 24BIT 104DB 32QFN
CS4270-DZZ IC CODEC 24BIT 105DB 24TSSOP
CS4271-DZZ IC CODEC 24BIT 114DB 28-TSSOP
CS4272-DZZ IC CODEC 24BIT 114DB 28-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS4205-KQZR 功能描述:接口—CODEC IC AC’97 Codec for Docking Stations RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
CS4207 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
CS4207-CNZ 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
CS4207-CNZ/C1 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
CS4207-CNZR 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*