參數(shù)資料
型號： CS4205-KQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 50/81頁
文件大小： 0K
描述： IC CODEC AC97 I2S 48-LQFP
標(biāo)準(zhǔn)包裝： 250
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18，20 b
ADC / DAC 數(shù)量： 1 / 2
三角積分調(diào)變： 是
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 90 / 90
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 754 (CN2011-ZH PDF)
其它名稱： 598-1182
CS4205
54
DS489PP4
6. SERIAL DATA PORTS
6.1
Overview
The CS4205 implements two serial data output
ports and three serial data input ports that can be
used for digital docking or multi-channel expan-
sion. Each serial port consists of 4 signals: MCLK,
SCLK, LRCLK, and SDATA. The existing 256 Fs
BIT_CLK will be used as MCLK. The clock pins
are shared between all the serial ports with only the
SDATA pins being separate; SDOUT for the first
output port, SDO2 for the second output port, and
SDI[3:1] for the three input ports. Serial data is re-
ceived and transmitted on these ports every
AC-link frame.
The serial data port is controlled by the SDEN,
SDSC, SDI[3:1], and SDO2 bits in the Serial Port
Control Register (Index 6Ah). All the serial data
port pins are multiplexed with other functions and
cannot be used unless the other function is disabled
or powered down; see Section 9, Exclusive Func-
tions. Some audio DACs can run in an internal
SCLK mode where SCLK is internally derived
from MCLK and LRCLK. In this case, SCLK gen-
eration in the CS4205 is optional.
A feature has been designed into the CS4205 that
allows the phase of the internal DACs to be re-
versed. This DAC phase reversal is controlled by
(Index 60h). This feature is necessary since the
phase response for external DACs is unknown and
the phase response of the internal DACs can vary
depending on the path determined by the DDM bit
in the AC Mode Control Register (Index 5Eh). This
feature guarantees that all DACs in a system have
the same phase response, maintaining the accuracy
of spatial cues.
In the CS4205, the volume of the serial port data is
controlled with the Serial Data Port Volume Con-
trol Registers (Index 6Eh, Address 06h - 07h).
However, there is no SRC available on this data, so
it is the responsibility of the controller or host soft-
ware to provide this functionality if desired.
6.2
Multi-Channel Expansion
For multi-channel expansion, the two serial data
output ports are used to send AC-link data to one or
two external stereo DACs to support up to a total of
six channels. The first serial port takes the digital
audio data from the SDOUT slots. The second seri-
al port takes the digital audio data from the SDO2
slots. See Table 14 on page 43 for the actual slots
used depending on configuration. Figure 15 shows
a six channel application using the CS4205.
8
5
4
3
2
1
4
3
2
18
5
AOUTL
AOUTR
SDATA
DEM#/SCLK
LRCK
MCLK
GPIO1/SDOUT
SPDO/SDO2
44
48
47
43
EAPD/SCLK
GPIO0/LRCLK
LINE_OUT_L
LINE_OUT_R
BIT_CLK
6
36
35
CS4334
AOUTL
AOUTR
SDATA
DEM#/SCLK
LRCK
MCLK
CS4334
270K
10uF
ELEC
10uF
ELEC
47K
560
2700pF 2700pF
Left Surround
Right Surround
270K
10uF
ELEC
10uF
ELEC
47K
560
2700pF 2700pF
Center
LFE
AGND
Left Front
Right Front
AGND
10uF
ELEC
10uF
ELEC
1000pF
AGND
220K
AGND
1000pF
+
Figure 15. Serial Data Port: Six Channel Circuit
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