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參數(shù)資料
| 型號： | CS4207-DNZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 26/77頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUD HDPN AMP AUTO 48QFN |
| 標(biāo)準(zhǔn)包裝： | 429 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 3 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 105 / 110 |
| 電壓 - 電源，模擬： | 2.97 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.97 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-QFN |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 598-1798 |
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32
DS880F4
CS4207
If the codec has detected that the link is entering a Link Reset state (see description below), all Unsolicited
Response requests will be buffered. Once the link is in the Link Reset state, with RESET# asserted low,
the codec will request a power state change and initialization request. Following the codec initialization
cycle where a unique address is provided to the CS4207, the codec will then wait for the first verb to be
received before issuing the Unsolicited Response to prevent the response from being lost due to software
transition to active power state.
The Link Reset entry sequence is defined as follows:
1.
The HD Audio Bus controller synchronously completes the current frame but does not signal Frame
Sync (SYNC) during the last eight SDO bit times.
2.
The HD Audio Bus controller synchronously asserts RESET# four (or more) BITCLK cycles after the
completion of the current frame.
3.
BITCLK is stopped a minimum of four clocks, four rising edges, after the assertion of RESET#.
In the event of a system bus (PCI Bus) reset, the above sequence does not complete, and RESET# is
asynchronously asserted immediately and unconditionally.
When the codec returns to D0 from the D3 lower power state, the state of the presence detection bits will
be correct. If the codec power has been removed, the state of the presence detection bits will be reset to
the default value and the codec
WILL NOT report this by setting the PS-SettingsReset bit for the affected
Pin Widget(s). (HDA015-B, March 1, 2007 says that the PS-SettingsReset bit will be set for the affected
Pin widget).
5.1.2
S/PDIF Receiver Presence Detect
The presence detect scheme for the S/PDIF Receiver will use the logic state transition of the “LOCK” or
“UNLOCK” indicator for the incoming digital stream. The “LOCK” and “UNLOCK” indicators are sticky bits
(edge-triggered) which indicate the current state of the receiver. These bits are located in the Vendor Pro-
cessing Widget, see “S/PDIF RX/TX Interface Status (CIR = 0000h)” on p 129. When the S/PDIF Receiver
Input Converter Widget is “enabled” and the “LOCK” indicator is a “1”, then the Presence Detect bit in the
Pin Sense register will be set to ‘1’. The S/PDIF IN Converter Widget (NID=07h) and the S/PDIF Receiver
pin widget (NID=0Fh) must be in the D0 state to support presence detect using this method described.
With an incoming valid S/PDIF signal applied to the SPDIF_IN pin, the “LOCK” status will be valid approx-
imately 200 S/PDIF frames following the receiver being enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4207-DNZR | 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42080DR8 | 制造商:ON Semiconductor 功能描述: |
| CS4210 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IEEE 1394 OHCI Controller |
| CS4210A-CNZ | 制造商:Cirrus Logic 功能描述:IC LOW POWER HD AUDIO CODEC - Bulk 制造商:Cirrus Logic 功能描述:HD CODEC |
| CS4210A-CNZR | 功能描述:IC LOW POWER HD AUDIO CODEC RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:* 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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