參數(shù)資料
型號: CS4265-CNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 21/46頁
文件大?。?/td> 0K
描述: IC CODEC 24BIT 104DB 32QFN
標(biāo)準(zhǔn)包裝: 60
類型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 104 / 104
電壓 - 電源,模擬: 3.13 V ~ 5.25 V
電壓 - 電源,數(shù)字: 3.13 V ~ 5.25 V
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-QFN
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
配用: 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
其它名稱: 598-1039
28
DS657F3
CS4265
topology. If pseudo-differential input functionality is not required, simply connect the SGND pin to AGND
through the parallel combination of a 10 F and a 0.1 F capacitor.
4.6
Output Connections
The CS4265 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with tha t of the digital interpolator, is sh own in Section 8. “DAC Filter Plots” on
page 48”. The recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4265 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
4.7
Output Transient Control
The CS4265 uses Popguard technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended, single-
supply converters when it is implemented with external DC-blocking capacitors connected in series with the
audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1
Power-Up
When the device is initially powered-up, the DAC outputs AOUTA and AOUTB are clamped to VQ, which
is initially low. After the PDN bit is released (set to ‘0’), the outputs begin to ramp with VQ towards the
nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui-
escent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2
Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this, either the PDN should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VQ and the DAC outputs will gradually
discharge to GND. If power is removed before this 250 ms time period has passed, a transient will occur
when the VA supply drops below that of VQ. There is no minimum time for a power cycle; power may be
re-applied at any time.
4.7.3
Serial Interface Clock Changes
When changing the clock ratio or sample rate, it is recommended that zero data (or near zero data) be
present on the selected SDIN pin for at least 10 LRCK samples before the change is made. During the
+
-
VA
+
-
AINA
AINB
SG ND
In to PG A
10 F
0.1 F
Note: If pseudo-differential input functionality is not required, the
connections shown with dashed line should be added.
Figure 12. Pseudo-Differential Input Stage
CS4265
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CS4265-CNZ/C1 制造商:Cirrus Logic 功能描述:
CS4265-CNZR 功能描述:接口—CODEC IC 24bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
CS4265-DNZ 功能描述:接口—CODEC Stereo Audio CODEC 104 dB 192 kHz RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
CS4265-DNZR 功能描述:接口—CODEC IC 24-bit 192kHz Str Cdc w/PGA &Inpt Mux RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
CS4267AM 制造商:Rochester Electronics LLC 功能描述:- Bulk