4.7 Microphone Volume Register (Index 0Eh) Mute Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection" />
參數(shù)資料
型號: CS4299-JQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 16/52頁
文件大?。?/td> 0K
描述: IC CODEC AC 97 W/SRC 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: SoundFusion™
類型: 音頻編解碼器 '97
數(shù)據(jù)接口: 串行
分辨率(位): 18 b,20 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 87
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
CS4299
23
4.7
Microphone Volume Register (Index 0Eh)
Mute
Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or
MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h).
GN[4:0]
Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Micro-
phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with
01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 3 for further details.
20dB
Microphone 20 dB Boost. When ‘set’, the 20dB bit enables the +20 dB microphone boost block.
This bit allows for variable boost of 0 dB or +20 dB. Table 3 summarizes this behavior.
Default
8008h. This value corresponds to 0 dB gain and Mute ‘set’.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
00
20dB
0
GN4
GN3
GN2
GN1
GN0
GN[4:0]
Gain Level
20dB = 0
20dB = 1
00000
+12.0 dB
+32.0 dB
00001
+10.5 dB
+30.5 dB
……
...
00111
+1.5 dB
+21.5 dB
01000
0.0 dB
+20.0 dB
01001
-1.5 dB
+18.5 dB
……
...
11111
-34.5 dB
-14.5 dB
Table 3. Microphone Input Gain Values
DS319PP6
23
CS4299
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