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參數(shù)資料
| 型號： | CS4299-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 8/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AC 97 W/SRC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SoundFusion™ |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 18 b，20 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 85 / 87 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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CS4299
16
3.2
AC-Link Audio Input Frame
In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299 to the AC ’97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus-
trates the serial port timing.
The PCM capture data from the CS4299 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun-
cate) to the desired bit depth.
Bits that are reserved or not implemented in the CS4299 will always be returned ‘cleared’.
3.2.1
Serial Data Input Slot Tag Bits (Slot 0)
Codec Ready
The Codec Ready bit indicates the readiness of the CS4299 AC-link. Immediately after a Cold
Reset this bit will be ‘clear’. Once the CS4299 clocks and voltages are stable, this bit will be
‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the
controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any
other analog function. Those must be checked in the Powerdown Control/Status Register (In-
dex 26h) by the controller before any access is made to the mixer registers. Any accesses to
the CS4299 while Codec Ready is ‘clear’ are ignored.
Slot 1 Valid
When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.
Slot 2 Valid
When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.
Slot [3:10] Valid
When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the
CS4299 ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot contain
valid data.
3.2.2
Status Address Port (Slot 1)
RI[6:0]
Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has
been requested in the previous frame. The CS4299 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.
SR[3:10]
Slot Request. If SRx is ‘set’, this indicates the CS4299 SRC does not need a new sample on
the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is ‘clear’, the SR[3:10] bits are always 0. When VRA is ‘set’, the SRC is enabled
and the SR[3:10] bits are used to request data.
Bit 15
14
13
12
11
10
9
8
76
543210
Codec
Ready
Slot 1
Valid
Slot 2
Valid
Slot 3
Valid
Slot 4
Valid
Slot 5
Valid
Slot 6
Valid
Slot 7
Valid
Slot 8
Valid
Slot 9
Valid
Slot 10
Valid
00000
Bit 19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3210
0
RI6
RI5
RI4
RI3
RI2
RI1
RI0
SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10
0
Reserved
16
DS319PP6
CS4299
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